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* OpenSPARC T2 Processor File: n2_err_l2_LDRU_cecc_trap.s
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#define ENABLE_PCIE_LINK_TRAINING
#define MAIN_PAGE_HV_ALSO
#define L2_ENTRY_PA 0xa000000000
#define TEST_DATA1 0x5555555555555555
#define L2_ENTRY_PA0 0x30000008
#define L2_ES_W1C_VALUE 0xc03ffff800000000
#define SPARC_ES_W1C_VALUE 0xefffffff
#define DMA_DATA_BYP_ADDR1 0xfffc000030aa0000
! Boot code does not provide TLB translation for IO address space
ldxa [%g0] ASI_LSU_CONTROL, %l0
stxa %l0, [%g0] ASI_LSU_CONTROL
setx L2_ES_W1C_VALUE, %l0, %l1
set_L2_Directly_Mapped_Mode:
setx L2CS_PA0, %l6, %g1 ! Bit 1 in L2 Control Status Register
setx TEST_DATA1, %l0, %g5
set 0x30aa0000, %g2 ! bits [21:18] select way
setx 0x3ffff8, %l0, %l2 ! Mask for extracting [21:3]
setx L2_ENTRY_PA, %l0, %g4
and %g2, %l2, %g5 !g2 has L2 PA,
or %g5, %g4, %g5 !g5 now has Diagnostic Data Array address
! Flip two bits to inject error
! $EV trig_pc_d(1, @VA(.MAIN.PIO2_noexp)) -> EnablePCIeIgCmd ("PIO_NOEXP",0,0,0,1)
PIO2: nop; nop; nop; nop; nop; nop; nop; nop;
! $EV trig_pc_d(1, @VA(.MAIN.Wr_Evnt) -> EnablePCIeIgCmd ("DMARD_UE", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1 )
! $EV trig_pc_d(1, @VA(.MAIN.PIO3_noexp)) -> EnablePCIeIgCmd ("PIO_NOEXP",0,0,0,1)
PIO3: nop; nop; nop; nop; nop; nop; nop; nop;
! $EV trig_pc_d(1, @VA(.MAIN.Wr_Evnt_mec) -> EnablePCIeIgCmd ("DMARD_UE", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1 )
! sllx %g4, L2ES_TID, %l3 ! ID of thread that encountered error
! or %l7, %l3, %l7 ! %l7 has expected value
cmp %l7, %l4 ! l7 has expected value l4 has actula value
ldxa [%g0] ASI_LSU_CONTROL, %l0
stxa %l0, [%g0] ASI_LSU_CONTROL
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