* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: n2_err_adv_mcu_3.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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* ========== Copyright Header End ============================================
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO
#define L2_ERR_STAT_REG 0xAB00000000
#define L2_ERR_ADDR_REG 0xAC00000000
#define TEST_DATA1 0x1000100081c3e008
#define TEST_DATA2 0x2000200081c3e008
#define L2_ES_W1C_VALUE 0xc03ffff800000000
#define DRAM_ES_W1C_VALUE 0xfe00000000000000
#define DRAM_ERR_INJ_REG 0x8400000290
#define DRAM_ERR_STAT_REG 0x8400000280
#define ERROR_ADDR 0x20200000
#define DRAM_SCRUB_FREQ_REG 0x8400000018
#define DRAM_SCRUB_ENB_REG 0x8400000040
ldxa [%g0] ASI_LSU_CONTROL, %l0
! Remove the lower 2 bits (I-Cache and D-Cache enables)
stxa %l0, [%g0] ASI_LSU_CONTROL
setx DRAM_ES_W1C_VALUE, %l0, %g2
setx 0x8400000280, %l1, %g6
setx L2_ES_W1C_VALUE, %l0, %g4
setx 0xbb00000000, %l1, %g7
brnz %g3,ld_from_L2_bank0
check_DRAM_ESR_MCU0_DAC_and_MEC_B0:
check_L2_ESR_Bank_0_DAC_and_MEC:
setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
setx DRAM_ES_W1C_VALUE, %l0, %g2
setx 0x8400000280, %l1, %g6
setx L2_ES_W1C_VALUE, %l0, %g4
setx 0xbb00000040, %l1, %g7
brnz %g3,ld_from_L2_bank1
check_DRAM_ESR_MCU0_DAC_and_MEC_B1:
check_L2_ESR_Bank_1_DAC_and_MEC:
setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
setx DRAM_ES_W1C_VALUE, %l0, %g2
setx 0x8400001280, %l1, %g6
setx L2_ES_W1C_VALUE, %l0, %g4
setx 0xbb00000080, %l1, %g7
brnz %g3,ld_from_L2_bank2
check_DRAM_ESR_MCU1_DAC_and_MEC_B2:
check_L2_ESR_Bank_2_DAC_and_MEC:
setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
setx DRAM_ES_W1C_VALUE, %l0, %g2
setx 0x8400001280, %l1, %g6
setx L2_ES_W1C_VALUE, %l0, %g4
setx 0xbb000000c0, %l1, %g7
brnz %g3,ld_from_L2_bank3
check_DRAM_ESR_MCU1_DAC_and_MEC_B3:
check_L2_ESR_Bank_3_DAC_and_MEC:
setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
setx DRAM_ES_W1C_VALUE, %l0, %g2
setx 0x8400002280, %l1, %g6
setx L2_ES_W1C_VALUE, %l0, %g4
setx 0xbb00000100, %l1, %g7
brnz %g3,ld_from_L2_bank4
check_DRAM_ESR_MCU2_DAC_and_MEC_B4:
check_L2_ESR_Bank_4_DAC_and_MEC:
setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
setx DRAM_ES_W1C_VALUE, %l0, %g2
setx 0x8400002280, %l1, %g6
setx L2_ES_W1C_VALUE, %l0, %g4
setx 0xbb00000140, %l1, %g7
brnz %g3,ld_from_L2_bank5
check_DRAM_ESR_MCU2_DAC_and_MEC_B5:
check_L2_ESR_Bank_5_DAC_and_MEC:
setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
setx DRAM_ES_W1C_VALUE, %l0, %g2
setx 0x8400003280, %l1, %g6
setx L2_ES_W1C_VALUE, %l0, %g4
setx 0xbb00000180, %l1, %g7
brnz %g3,ld_from_L2_bank6
check_DRAM_ESR_MCU3_DAC_and_MEC_B6:
check_L2_ESR_Bank_6_DAC_and_MEC:
setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
setx DRAM_ES_W1C_VALUE, %l0, %g2
setx 0x8400003280, %l1, %g6
setx L2_ES_W1C_VALUE, %l0, %g4
setx 0xbb000001c0, %l1, %g7
brnz %g3,ld_from_L2_bank7
check_DRAM_ESR_MCU3_DAC_and_MEC_B7:
check_L2_ESR_Bank_7_DAC_and_MEC:
setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
/*******************************************************
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