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* OpenSPARC T2 Processor File: n2_err_dram_dac_dau_fbr.s
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* ========== Copyright Header End ============================================
#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO
#define DRAM_ERR_INJ_REG 0x8400000290
#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_0
#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_0
#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_0
#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_0
#define DRAM_ERR_INJ_REG 0x8400000290
#define DRAM_ERR_STAT_REG 0x8400000280
#define L2_ERR_STAT_REG 0xAB00000000
#define L2_ERR_ADDR_REG 0xAC00000000
#define L2_BANK_ADDR 0x80
#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_1
#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_1
#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_1
#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_1
#define DRAM_ERR_INJ_REG 0x8400001290
#define DRAM_ERR_STAT_REG 0x8400001280
#define L2_ERR_STAT_REG 0xAB00000080
#define L2_ERR_ADDR_REG 0xAC00000080
#define L2_BANK_ADDR 0x100
#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_2
#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_2
#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_2
#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_2
#define DRAM_ERR_INJ_REG 0x8400002290
#define DRAM_ERR_STAT_REG 0x8400002280
#define L2_ERR_STAT_REG 0xAB00000100
#define L2_ERR_ADDR_REG 0xAC00000100
#define L2_BANK_ADDR 0x180
#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_3
#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_3
#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_3
#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_3
#define DRAM_ERR_INJ_REG 0x8400003290
#define DRAM_ERR_STAT_REG 0x8400003280
#define L2_ERR_STAT_REG 0xAB00000180
#define L2_ERR_ADDR_REG 0xAC00000180
.global My_Corrected_ECC_error_trap
.global My_Recoverable_Sw_error_trap
! Now access L2 control and status registers
ldxa [%g0] ASI_LSU_CONTROL, %l0
! Remove the lower 2 bits (I-Cache and D-Cache enables)
stxa %l0, [%g0] ASI_LSU_CONTROL
set_L2_Direct_Mapped_Mode:
set_DRAM_error_inject_ch0:
mov 0x2, %l1 ! ECC Mask (1-bit error)
sllx %l2, DRAM_EI_SSHOT, %l3
or %l1, %l3, %l1 ! Set single shot ;
sllx %l2, DRAM_EI_ENB, %l3
or %l1, %l3, %l1 ! Enable error injection for the next write
setx DRAM_ERR_INJ_REG, %l3, %g6
! add %g6, MCU_BANK_ADDR, %g6
setx 0x555555555, %l0, %g5
setx 0x22000000, %l0, %g7 ! bits [21:18] select way
add %g7, L2_BANK_ADDR, %g7
! Storing to same L2 way0 but different tag,this will write to mcu
setx 0x31000000, %l0, %g3 ! bits [21:18] select way
add %g3, L2_BANK_ADDR, %g3
set_DRAM_error_inject_ch0_dau:
mov 0x606, %l1 ! ECC Mask (1-bit error)
sllx %l2, DRAM_EI_SSHOT, %l3
or %l1, %l3, %l1 ! Set single shot ;
sllx %l2, DRAM_EI_ENB, %l3
or %l1, %l3, %l1 ! Enable error injection for the next write
setx DRAM_ERR_INJ_REG, %l3, %g6
! add %g6, MCU_BANK_ADDR, %g6
setx 0x555555555, %l0, %g5
setx 0x11000000, %l0, %g7 ! bits [21:18] select way
add %g7, L2_BANK_ADDR, %g7
! Storing to same L2 way0 but different tag,this will write to mcu
setx 0x32000000, %l0, %g3 ! bits [21:18] select way
add %g3, L2_BANK_ADDR, %g3
set 0x10000, %g6 !<16>=countone=1
setx DRAM_FBR_CNT_REG_PA, %l7, %o2
set 0x1, %g6 !<16>=countone=1
setx DRAM_ERR_CNT_REG_PA, %l7, %o2
setx SOC_ESR_REG, %l7, %g5
setx SOC_PER_REG, %l7, %g5
setx DRAM_ERR_STAT_REG, %l7, %g5
setx L2_ERR_STAT_REG, %l7, %g5
setx L2_ERR_ADDR_REG, %l7, %g5
setx DRAM_FBD_INJ_ERR_SRC_REG_PA, %l7, %g3
setx SOC_EJR_REG, %l7, %g3
setx SOC_EIE_REG, %l7, %g3
read_error_address_ch0_FBR:
setx 0xfffffffffff,%l0,%l1
setx 0x12345678910,%l0,%l1
setx 0x55555555555,%l0,%l1
setx 0x66666666666,%l0,%l1
setx 0x77777777777,%l0,%l1
setx 0x88888888888,%l0,%l1
setx 0xfffffffffff,%l0,%l1
/******************************************************
*******************************************************/
/************************************************************************
************************************************************************/
My_Recoverable_Sw_error_trap:
!PER not cleared at the end of the TRAP Handler to avoid further Trap
My_Corrected_ECC_error_trap:
setx SOC_EJR_REG, %l7, %l0
setx 0x8b00000000000000, %l0, %g3
sllx %l1, DRAM_ES_FBR, %l6
sllx %l1, DRAM_ES_DAU, %l3
sllx %l1, DRAM_ES_DAC, %l3
setx DRAM_ERR_STAT_REG, %l3, %g5
setx 0xbfffffffffff0000, %l3, %l0 ! MEC bit not checked
setx DRAM_ERR_ADDR_REG_PA_0, %l3, %g5
! Setting DSC and/ or DSU does not cause any logging of the error
! address or syndrome in the L2 Error Address register.
! It also does not update the VEC/VEU/MEC/MEU bits */
setx L2_ERR_STAT_REG, %l3, %g5
setx 0xbffffffff0000000, %l3, %l0
andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits and MEC
setx DRAM_FBR_CNT_REG_PA, %l7, %o2
set 0x10000, %g6 !<16>=countone=1
setx DRAM_ERR_CNT_REG_PA, %l7, %o2
read_fbd_err_synd_reg_tt63:
setx DRAM_FBD_ERR_SYND_REG_PA, %l7, %o2
setx 0x8000000000000000, %l7, %o3
setx SOC_PER_REG, %l7, %l0
setx SOC_ESR_REG, %l7, %l0