* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: n2_err_ncu_peu_piowr.s
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* ========== Copyright Header End ============================================
#define ENABLE_PCIE_LINK_TRAINING
/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
#define MAIN_PAGE_HV_ALSO
!#define IO_WR_ADDR mpeval(N2_PCIE_BASE_ADDR + IOCFG_OFFSET_BASE_REG_DATA)
#define IO_WR_ADDR mpeval((N2_PCIE_BASE_ADDR + IOCFG_OFFSET_BASE_REG_DATA) | IO_ACCESS_PA)
/************************************************************************
************************************************************************/
setx SOC_ESR_REG, %l7, %i0
setx SOC_EJR_REG, %l7, %i3
/******************************
******************************/
setx SOC_ESR_REG, %l7, %i0
setx 0x8000000000000000, %l7, %o3 !valid bit
/********************************/
/************************************************************************
************************************************************************/
SECTION .DATA DATA_VA=IO_WR_ADDR
/************************************************************************/