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* OpenSPARC T2 Processor File: n2_err_siu_dmu_trap.s
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#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
#define MAIN_PAGE_HV_ALSO
!#include "dmu_peu_regs.h"
#define CFG_RD_ADDR mpeval(N2_PCIE_BASE_ADDR + IOCFG_OFFSET_MASK_REG_DATA)
#define CFG_RD_DATA 64'h33323130
/************************************************************************
************************************************************************/
.global My_Corrected_ECC_error_trap
.global My_Recoverable_Sw_error_trap
CONFIGURE_NCU_FOR_PCIE_TRAFFIC:
setx IOCFG_OFFSET_BASE_REG_ADDR, %g1, %g2
setx IOCFG_OFFSET_BASE_REG_DATA, %g1, %g3
setx IOCFG_OFFSET_MASK_REG_ADDR, %g1, %g2
setx IOCFG_OFFSET_MASK_REG_DATA, %g1, %g3
setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
setx SOC_EJR_REG, %l7, %i3
setx SOC_EIE_REG, %l7, %g5
nop ! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt)) -> EnablePCIeIgCmd ("DMAWR", IOMMU_BYP_SADDR, IOMMU_BYP_SADDR, 64'h40, 64'd1 )
! select a CFG address in PCI address range and transmit the command to NCU
setx CFG_RD_ADDR, %g1, %g2
setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g2
! but the next error causes it to log again;
! Get from Uday a diag which has just 1 DMA
setx SOC_ESR_REG, %l7, %i0
setx 0x8000000000000000, %l7, %o3 !valid bit
setx SOC_PER_REG, %l7, %i0
! Check if a Corrected ECC Trap happened
setx SOC_ESR_REG, %l7, %i0
setx 0x8000000000000000, %l7, %o3 !valid bit
/************************************************************************
************************************************************************/
My_Recoverable_Sw_error_trap:
My_Corrected_ECC_error_trap:
/************************************************************************
************************************************************************/
/************************************************************************/