* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: interrupt_niu_sys_data.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
* available with the language indicating that GPLv2 or any later version
* may be used, or where a choice of which version of the GPL is applied is
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
* CA 95054 USA or visit www.sun.com if you need additional information or
* ========== Copyright Header End ============================================
#define MAIN_PAGE_HV_ALSO
#define H_HT0_Interrupt_0x60
#define My_HT0_Interrupt_0x60 \
/************************************************************************
************************************************************************/
/* Initialize the NCU for the interrupt. */
xor %g7, 0x2, %g7 ! Reset interrupt enable
! Initially set all the Interrupt Management Registers
setx INT_MAN, %g1, %g2 ! %g2 = INT_MAN reg. addr.
setx INT_MAN_COUNT, %g1, %g4 ! %g4 = INT_MAN reg. count value
add %g2, INT_MAN_STEP, %g2
add %g2, INT_MAN_STEP, %g2
add %g5, 1, %g5 ! increment the vector number
/* Initialize the NIU for TX DMA interrupt. */
NIU_TX_LD_IM0_INTR_ON_MARK( 0, %g1, %g2, %g3, %g4, 0, 0x40 )
or %g7, 0x2, %g7 ! Set interrupt enable
nop ! $EV trig_pc_d(1, @VA(.MAIN.Init_flow)) -> pktGenConfig(MAC_ID, FRAME_TYPE, FRAME_CLASS,TX_PKT_LEN)
setx MAC_ID, %g1, %o0 ! 1st Parameter
setx SetTxDMAActive_list, %g1, %o1 ! 2st parameter
nop ! $EV trig_pc_d(1, @VA(.MAIN.P_TxDMAActivate)) -> NIU_TxDMAActivate (MAC_ID, TxDmaActive_list)
nop ! $EV trig_pc_d(1, @VA(.MAIN.P_AddTxChannels)) -> NIU_AddTxChannels(MAC_ID, NIU_TxDmaNoUE)
ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter :
setx SetTxMaxBurst_Data, %g1, %o1 ! 2nd parameter
nop ! $EV trig_pc_d(1, @VA(.MAIN.P_SetTxMaxBurst)) -> NIU_SetTxMaxBurst (MAC_ID, NIU_TxDmaNoUE, TxMaxBurst_Data)
ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter :
nop ! $EV trig_pc_d(1, @VA(.MAIN.P_InitTxDma)) -> NIU_InitTxDma (MAC_ID, NIU_TxDmaNoUE, NIU_Xlate_On)
ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
nop ! $EV trig_pc_d(1, @VA(.MAIN.Gen_Packet)) -> TxPktGen(MAC_ID, NIU_TxDmaNoUE,NIU_TX_PKT_CNT,0,0)
ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick)) -> NIU_SetTxRingKick(MAC_ID, NIU_TxDmaNoUE)
setx NIU_TxDmaNo, %g1, %o0
setx TX_RING_KICK_Addr, %g1, %g2
stxa %g3, [%g2]ASI_PRIMARY_LITTLE
setx NIU_TxDmaNo, %g1, %o0
setx TX_CS_Data, %g1, %g3
setx TX_CS_Addr, %g1, %g2
stxa %g3, [%g2]ASI_PRIMARY_LITTLE
#ifdef JUMBO_FRAME_EN /* Extra Delay for Jumbo packets to go out */
setx loop_count, %g1, %g4
ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
! Wait for the interrupt to occur.
setx user_data_start, %g1, %g5
ba local_test_failed ! timeout waiting for interrupt
st %g7, [%g3] ! undate old_intr_count
! Check the packet count.
setx NIU_TX_PKT_CNT, %g1, %o1
setx loop_count, %g1, %g4
ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
nop ! $EV trig_pc_d(1, @VA(.MAIN.test_passed)) -> NIU_EXIT_chk(MAC_ID)
! Read related interrupt registers to aid debugging
ldxa [%g0]ASI_INTR_RECEIVE, %i0
ldxa [%g0]ASI_SWVR_INTR_R, %i1
set 32, %g3 ! index for logical device number
setx LDG_NUM_STEP, %g1, %g4
ldxa [%g2]ASI_PRIMARY_LITTLE, %i3
ldxa [%g2]ASI_PRIMARY_LITTLE, %i4
ldxa [%g2]ASI_PRIMARY_LITTLE, %i5
ldxa [%g2]ASI_PRIMARY_LITTLE, %i6
set 32, %g3 ! index for logical device number
setx LD_IM0_STEP, %g1, %g4
ldxa [%g2]ASI_PRIMARY_LITTLE, %i7
ldxa [%g2]ASI_PRIMARY_LITTLE, %o1
ldxa [%g2]ASI_PRIMARY_LITTLE, %o2
ldxa [%g2]ASI_PRIMARY_LITTLE, %o3
setx TX_ENT_MSK, %g1, %g2
ldxa [%g2]ASI_PRIMARY_LITTLE, %o4
ldxa [%g2]ASI_PRIMARY_LITTLE, %o5
setx TDMC_INTR_DBG, %g1, %g2
ldxa [%g2]ASI_PRIMARY_LITTLE, %o6
/**********************************************************************
**********************************************************************/
setx user_data_start, %l2, %l6
! Check the expected vector number and clear the interrupt in the core.
ldxa [%g0]ASI_INTR_R, %l7
! The following order is important, if reversed a second
! interrupt occurs on same condition.
! Re-enable the interrupt in the transmit DMA channel
setx TX_CS, %g1, %g2 ! TX_CS, Tx DMA channel 0
ldxa [%g2]ASI_PRIMARY_LITTLE, %g1 ! Reset MK
! Re-enable the interrupt in the NIU
setx LDGIMGN, %g1, %g2 ! logical device group 0
setx 0x80000001, %g1, %g3
stxa %g3, [%g2]ASI_PRIMARY_LITTLE
/************************************************************************
************************************************************************/
/* These initialization is temporary, as there looks some bug in mempli */
SECTION SetRngConfig_init data_va=0x100000000
Name = SetRngConfig_init,
.xword 0x0060452301000484
/************************************************************************/
SECTION SetTxRingKick_init data_va=0x100000100
Name = SetTxRingKick_init,
.xword 0x0060452301000484
/************************************************************************/
SECTION SetTxLPMask1_init data_va=0x100000200
Name = SetTxLPMask1_init,
.xword 0x0060452301000484
/************************************************************************/
SECTION SetTxLPValue1_init data_va=0x100000300
Name = SetTxLPValue1_init,
.xword 0x0060452301000484
/************************************************************************/
SECTION SetTxLPRELOC1_init data_va=0x100000400
Name = SetTxLPRELOC1_init,
.xword 0x0060452301000484
/************************************************************************/
SECTION SetTxLPMask2_init data_va=0x100000500
Name = SetTxLPMask2_init,
.xword 0x0060452301000484
/************************************************************************/
SECTION SetTxLPValue2_init data_va=0x100000600
Name = SetTxLPValue2_init,
.xword 0x0060452301000484
/************************************************************************/
SECTION SetTxLPRELOC2_init data_va=0x100000700
Name = SetTxLPRELOC2_init,
.xword 0x0060452301000484
/************************************************************************/
SECTION SetTxLPValid_init data_va=0x100000800
Name = SetTxLPValid_init,
.xword 0x0060452301000484
/************************************************************************/