* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: interrupt_pci_INTx_all_threads.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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* ========== Copyright Header End ============================================
#define MAIN_PAGE_HV_ALSO
#define ENABLE_PCIE_LINK_TRAINING
#define H_HT0_Interrupt_0x60
#define My_HT0_Interrupt_0x60 \
/************************************************************************
************************************************************************/
! Initialize the global registers.
mov %o1, %g6 ! %o1, %g6 = thread ID
setx user_data_start, %g1, %g3
add %l7, %g3, %g7 ! %g7 = pointer to thread's data area
be main_t0 ! branch if tread 0
ba main_t1_to_t63 ! branch if not thread 0
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
stx %g0, [%g7] ! Clear this thread's interrupt count
/* Initialize the NCU for the interrupt. */
xor %g7, 0x2, %g7 ! Reset interrupt enable
! Initially set all the Interrupt Management Registers
! Not used in this diag, so set vector number to 0, thread to 0.
setx INT_MAN, %g1, %g2 ! %g2 = INT_MAN reg. addr.
setx INT_MAN_COUNT, %g1, %g4 ! %g4 = INT_MAN reg. count value
add %g2, INT_MAN_STEP, %g2
! Initialize Mondo Interrupt Vector Register
setx MONDO_INT_VEC, %g2, %g3
! Clear Mondo Interrupt Busy registers.
setx MONDO_INT_BUSY, %g1, %g2
setx MONDO_INT_BUSY_STEP, %g1, %g3
setx MONDO_INT_BUSY_COUNT, %g1, %g4
ncu_mondo_int_busy_loop_top:
bne ncu_mondo_int_busy_loop_top
! Initialize for INTA interrupt in DMU/PEU
! First clear INTA in case one pending.
setx PCI_E_INT_A_CLEAR_ADDR, %g1, %g2
! Also clear in Interrupt Clear reg.
setx PCI_E_INT_CLEAR_ADDR, %g1, %g2
! Now enable INTA in DMU/PEU and set destination thread
setx PCI_E_INT_MAP_ADDR, %g1, %g7
setx 0x80000040, %g1, %g6 ! valid = 1, thread id = 0
ldxa [%g0]ASI_INTR_ID, %o2 ! get full thread ID
and %o2, 0x38, %o3 ! get thread 0 of this core
stx %g6, [%g7] ! interrupt controller = 1
or %g7, 0x2, %g7 ! Set interrupt enable
/* Sync up all the treads. */
SYNC_THREAD_MAIN( local_test_failed, %g1, %g2, %g3 )
! Kick off first interrupt, trap handler kicks off rest
! user event to generate ASSERT_INTA msg.
nop ! $EV trig_pc_d(1, @VA(.MAIN.first_inta_intr)) -> EnablePCIeIgCmd ("INTA", 0, 0, "ASSERT", 64'd1, *, * )
/* Wait for interrupt to occur. */
setx 0x2000, %g1, %g2 ! DTM timeout count
setx 0x800, %g1, %g2 ! timeout count
ta T_RD_THID ! %o1 = thread id
setx user_data_start, %g1, %g3
add %g7, %g3, %g7 ! %g7 = pointer to thread's data area
! Kick off next INTA interrupt
! user event for ASSERT_INTA msg.
nop ! $EV trig_pc_d(1, @VA(.MAIN.t0_new_intr)) -> EnablePCIeIgCmd ("INTA", 0, 0, "ASSERT", 64'd1, *, * )
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
! All Threads Except 0 Start Here
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
stx %g0, [%g7] ! Clear this thread's interrupt count
SYNC_THREAD_OTHER( %g6,%g1,%g2 )
/* Wait for interrupt to occur. */
setx 0x10000, %g1, %g2 ! DTM timeout count
setx 0x4000, %g1, %g2 ! timeout count
ta T_RD_THID ! %o1 = thread id
setx user_data_start, %g1, %g3
add %g7, %g3, %g7 ! %g7 = pointer to thread's data area
t1_t63_intr_wait_loop_top:
bne t1_t63_intr_wait_loop_top
! Kick off next INTA interrupt, if not in last thread
ldxa [%g0]ASI_INTR_ID, %o2 ! get full thread ID
! user event for ASSERT_INTA msg.
nop ! $EV trig_pc_d(1, @VA(.MAIN.t1_t63_new_intr)) -> EnablePCIeIgCmd ("INTA", 0, 0, "ASSERT", 64'd1, *, * )
/**********************************************************************
**********************************************************************/
ta T_RD_THID ! %o1 = thread id
ldxa [%g0]ASI_INTR_ID, %o2 ! get full thread ID
setx user_data_start, %l1, %l3
add %l7, %l3, %l7 ! %l7 = pointer to thread's data area
! Has interrupt to this thread already occured?
! Record interrupt occured for this thread.
! Check Mondo Interrupt Busy reg. for this thread
setx MONDO_INT_BUSY, %l1, %l2
setx MONDO_INT_BUSY_STEP, %l1, %l3
and %l4, 0x40, %l5 ! Is busy bit set?
! Check Mondo Interrupt Alias Busy reg.
setx MONDO_INT_ABUSY, %l1, %l2
cmp %l3, %l4 ! ABUSY = BUSY ?
! Check Mondo Interrupt Data 0/1 against Mondo Interrupt Alias Data 0/1
setx MONDO_INT_DATA0, %l1, %l2
setx MONDO_INT_DATA0_STEP, %l1, %l3
ldx [%l2], %l0 ! %l0 = mondo_int_busy0
setx MONDO_INT_ADATA0, %l1, %l4 ! %l5 = mondo_int_abusy0
setx MONDO_INT_DATA1, %l1, %l2
setx MONDO_INT_DATA1_STEP, %l1, %l3
ldx [%l2], %l0 ! %l0 = mondo_int_busy1
setx MONDO_INT_ADATA1, %l1, %l4 ! %l5 = mondo_int_abusy1
! Check INTA status in DMU/PEU
setx PCI_E_INT_CLEAR_ADDR, %l1, %l2
cmp %l0, 3 ! Should be in pending state
setx PCI_E_INTX_STATUS_ADDR, %l1, %l2
cmp %l0, 8 ! INTA should be only one active
setx PCI_E_INT_A_CLEAR_ADDR, %l1, %l2
cmp %l0, 1 ! INTA should be active
! Clear the INTA interrupt in the DMU/PEU
! user event for INTA deassert msg.
nop ! $EV trig_pc_d(1, @VA(.MAIN.trap_inta_clear)) -> EnablePCIeIgCmd ("INTA", 0, 0, "DEASSERT", 64'd1, *, * )
! Check the INTA status in INTA Clear reg.
setx 0x400, %l0, %l1 ! DTM Timeout count
setx 0x100, %l0, %l1 ! Timeout count
setx PCI_E_INT_A_CLEAR_ADDR, %l0, %l2
trap_inta_clear_loop_top:
cmp %l0, 0 ! Waiting for idle state
be local_test_failed ! Timeout check
ba trap_inta_clear_loop_top
! Check other DMU/PEU INTA registers
setx PCI_E_INTX_STATUS_ADDR, %l1, %l2
cmp %l0, 0 ! All should be inactive
setx PCI_E_INT_CLEAR_ADDR, %g1, %g2
! Clear the mondo interrupt in the NCU
setx MONDO_INT_ABUSY, %l0, %l1
cmp %l2, 0 ! Busy should be cleared
! Clear the interrupt in the core
ldxa [%g0]ASI_SWVR_INTR_R, %l5
cmp %l5, 63 ! check for correct vector number
! Increment the thread to send next interrupt to.
setx PCI_E_INT_MAP_ADDR, %l0, %l7
/************************************************************************
************************************************************************/
/************************************************************************/