* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: interrupt_pci_spurious_err.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
* available with the language indicating that GPLv2 or any later version
* may be used, or where a choice of which version of the GPL is applied is
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
* CA 95054 USA or visit www.sun.com if you need additional information or
* ========== Copyright Header End ============================================
#define MAIN_PAGE_HV_ALSO
#define H_HT0_Interrupt_0x60
#define My_HT0_Interrupt_0x60 \
/************************************************************************
************************************************************************/
stx %g0, [%g7] ! Clear this thread's interrupt count
/* Initialize the NCU for the interrupt. */
xor %g7, 0x2, %g7 ! Reset interrupt enable
! Initially set all the Interrupt Management Registers
! Not used in this diag, so set vector number to 1, thread to 0.
setx INT_MAN, %g1, %g2 ! %g2 = INT_MAN reg. addr.
setx INT_MAN_COUNT, %g1, %g4 ! %g4 = INT_MAN reg. count value
add %g2, INT_MAN_STEP, %g2
! Initialize Mondo Interrupt Vector Register
setx MONDO_INT_VEC, %g2, %g3
! Clear Mondo Interrupt Busy registers.
setx MONDO_INT_BUSY, %g1, %g2
setx MONDO_INT_BUSY_STEP, %g1, %g3
setx MONDO_INT_BUSY_COUNT, %g1, %g4
ncu_mondo_int_busy_loop_top:
bne ncu_mondo_int_busy_loop_top
! Initialize for error interrupt in PIU
! First clear error in case one pending.
setx PCI_E_MMU_ERR_STAT_CL_ADDR, %g1, %g2
! Also clear in Interrupt Clear reg.
setx PCI_E_INT_CLEAR_ADDR, %g1, %g2
setx PCI_E_INT_CLEAR_MONDO_62_OFFSET, %g1, %g4
! Now enable Mondo 62 in PIU and set destination thread
setx PCI_E_INT_MAP_ADDR, %g1, %g7
setx PCI_E_INT_MAP_MONDO_62_OFFSET, %g1, %g3
setx 0x80000040, %g1, %g6 ! valid = 1, thread id = 0
stx %g6, [%g7] ! interrupt controller = 1
! Enable MMU block mondo 62 interrupts
setx PCI_E_DMU_INT_ENB_ADDR, %g1, %g2
setx 0x8000000000000002, %g1, %g3 ! DMC = 1, MMU = 1
! Enable Bypass access with BE = 0 primary error
setx PCI_E_MMU_INT_ENB_ADDR, %g1, %g2
or %g7, 0x2, %g7 ! Set interrupt enable
/* Generate the error and therefore the interrupt */
setx PCI_E_MMU_ERR_STAT_SET_ADDR, %g1, %g2
/* Wait for two interrupts to occur */
setx 0x800, %g1, %g2 ! timeout count
setx user_data_start, %g1, %g3
/**********************************************************************
**********************************************************************/
ta T_RD_THID ! %o1 = thread id
! Check Mondo Interrupt Busy reg. for this thread
setx MONDO_INT_BUSY, %l1, %l2
setx MONDO_INT_BUSY_STEP, %l1, %l3
and %l4, 0x40, %l5 ! Is busy bit set?
! Check Mondo Interrupt Alias Busy reg.
setx MONDO_INT_ABUSY, %l1, %l2
cmp %l3, %l4 ! ABUSY = BUSY ?
! Check Mondo Interrupt Data 0/1 against Mondo Interrupt Alias Data 0/1
setx MONDO_INT_DATA0, %l1, %l2
setx MONDO_INT_DATA0_STEP, %l1, %l3
ldx [%l2], %l0 ! %l0 = mondo_int_busy0
setx MONDO_INT_ADATA0, %l1, %l4 ! %l5 = mondo_int_abusy0
setx MONDO_INT_DATA1, %l1, %l2
setx MONDO_INT_DATA1_STEP, %l1, %l3
ldx [%l2], %l0 ! %l0 = mondo_int_busy1
setx MONDO_INT_ADATA1, %l1, %l4 ! %l5 = mondo_int_abusy1
! Check error status in PIU
setx PCI_E_INT_CLEAR_ADDR, %l1, %l2
setx PCI_E_INT_CLEAR_MONDO_62_OFFSET, %l1, %l3
cmp %l0, 3 ! Should be in pending state
! MMU Interrupt Status reg.
setx PCI_E_MMU_INT_STAT_ADDR, %l1, %l2
! MMU Error Status Clear reg.
trap_mmu_err_status_clear:
setx PCI_E_MMU_ERR_STAT_CL_ADDR, %l1, %l2
! All status checking done.
! Only on second interrupt, clear the error, MMU Error Status Set reg.
setx user_data_start, %l2, %l6 ! Do not overwrite %l6 !
ldx [%l6], %l7 ! Do not overwrite %l7 !
bgt local_test_failed ! Should only get 2
! Clear error in MMU Error Status Set reg.
setx PCI_E_MMU_ERR_STAT_CL_ADDR, %l1, %l2
stx %l1, [%l2] ! RW1C reg.
membar #Sync ! Don't be hasty
! Clear the error, mondo 62 interrupt in the PIU, via Interrupt Clear reg.
setx PCI_E_INT_CLEAR_ADDR, %l0, %l2
setx PCI_E_INT_CLEAR_MONDO_62_OFFSET, %l1, %l3
membar #Sync ! Don't be hasty
! Clear the mondo interrupt in the NCU
setx MONDO_INT_ABUSY, %l0, %l1
cmp %l2, 0 ! Busy should be cleared
membar #Sync ! Don't be hasty
! Clear the interrupt in the core
ldxa [%g0]ASI_SWVR_INTR_R, %l5
cmp %l5, 63 ! check for correct vector number
! Indicate that the interrupt trap occured
/************************************************************************
************************************************************************/
/************************************************************************/