* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: memop_mcu_regs_rw.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
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* ========== Copyright Header End ============================================
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO
/************************************************************************
************************************************************************/
! DRAM_CAS_ADDR_WIDTH_REG
setx DRAM_CAS_ADDR_WIDTH_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
! DRAM_RAS_ADDR_WIDTH_REG
setx DRAM_RAS_ADDR_WIDTH_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_CAS_LAT_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_SCRUB_FREQ_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_REFRESH_FREQ_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_OPEN_BANK_MAX_REG, %g1, %g2
! DRAM_REFRESH_COUNTER_REG
setx DRAM_REFRESH_COUNTER_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_SCRUB_ENABLE_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
! DRAM_PROG_TIME_CNTR_REG
setx DRAM_PROG_TIME_CNTR_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_TRRD_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_TRC_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_TRCD_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_TWTR_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_TRTW_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_TRTP_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_TRAS_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_TRP_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_TWR_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_TRFC_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_TMRD_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_TIWTR_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
! DRAM_PRECHARGE_WAIT_REG
setx DRAM_PRECHARGE_WAIT_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_DIMM_STACK_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_EXT_WR_MODE2_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_EXT_WR_MODE1_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_EXT_WR_MODE3_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_8_BANK_MODE_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
! DRAM_CHANNEL_DISABLED_REG
setx DRAM_CHANNEL_DISABLED_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
! DRAM_SEL_LO_ADDR_BITS_REG
setx DRAM_SEL_LO_ADDR_BITS_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_DIMM_INIT_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_DIMM_PRESENT_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
! DRAM_FAILOVER_STATUS_REG
setx DRAM_FAILOVER_STATUS_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_FAILOVER_MASK_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
! DRAM_DEBUG_TRIG_ENABLE_REG
setx DRAM_DEBUG_TRIG_ENABLE_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_ERROR_STATUS_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_ERROR_ADDR_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_ERROR_INJECT_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_ERROR_COUNTER_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
! DRAM_ERROR_LOCATION_REG
setx DRAM_ERROR_LOCATION_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_PERF_CTL_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_PERF_COUNT_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx FBD_CHANNEL_STATE_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx FAST_RESET_FLAG_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx CHANNEL_RESET_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx TS1_SB_NB_MAPPING_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx TS1_TEST_PARAMETER_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
! TS3_FAILOVER_CONFIG_REG
setx TS3_FAILOVER_CONFIG_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
! DISABLE_STATE_PERIOD_REG
setx DISABLE_STATE_PERIOD_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
! CALIBRATE_STATE_PERIOD_REG
setx CALIBRATE_STATE_PERIOD_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
! TRAINING_STATE_MIN_TIME_REG
setx TRAINING_STATE_MIN_TIME_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
! TRAINING_STATE_DONE_REG
setx TRAINING_STATE_DONE_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
! TRAINING_STATE_TIMEOUT_REG
setx TRAINING_STATE_TIMEOUT_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx TESTING_STATE_DONE_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
! TESTING_STATE_TIMEOUT_REG
setx TESTING_STATE_TIMEOUT_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx POLLING_STATE_DONE_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
! POLLING_STATE_TIMEOUT_REG
setx POLLING_STATE_TIMEOUT_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx CONFIG_STATE_DONE_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
! CONFIG_STATE_TIMEOUT_PERIOD_REG
setx CONFIG_STATE_TIMEOUT_PERIOD_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx DRAM_PER_RANK_CKE_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx LOS_DURATION_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx SYNC_FRAME_FREQ_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
! CHANNEL_READ_LATENCY_REG
setx CHANNEL_READ_LATENCY_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx LOOPBACK_MODE_CTRL_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx SERDES_CONFIG_BUS_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
! SERDES_XMT_RCV_DIFF_INV_REG
setx SERDES_XMT_RCV_DIFF_INV_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx MCU_SYNDROME_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx INJ_ERR_SOURCE_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
setx MCU_FBR_COUNT_REG, %g1, %g2
setx DRAM_REG_STEP, %g1, %g3
/************************************************************************
************************************************************************/