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* OpenSPARC T2 Processor File: tcu_regs_dram_2.s
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#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO
#define TEST_DATA0 0x4c3fdead4c3fbeef
/************************************************************************
************************************************************************/
#define RESET_VEC 0x0000000000000000
#define RESET_VEC 0xfffffffff0000000
SECTION .RED_SEC TEXT_VA = RESET_VEC
! DRAM PRECHARGE COMMAND PERIOD
setx 0x8400000000, %l5, %l6
! DRAM WRITE RECOVER PERIOD
setx 0x8400000000, %l5, %l6
! DRAM AUTOREFRESH TO ACTIVE PERIOD
setx 0x8400000000, %l5, %l6
! DRAM MODE REG SET COMMAND PERIOD
setx 0x8400000000, %l5, %l6
! DRAM FOUR ACTIVE WINDOW
setx 0x8400000000, %l5, %l6
! DRAM INTERNAL WRITE TO READ COMMAND DELAY
setx 0x8400000000, %l5, %l6
! DRAM PRECHARGE WAIT DURING POWER UP
setx 0x8400000000, %l5, %l6
setx 0x8400000000, %l5, %l6
setx 0x8400000000, %l5, %l6
setx 0x8400000000, %l5, %l6
setx 0x8400000000, %l5, %l6
setx 0x8400000000, %l5, %l6
setx 0x8400000000, %l5, %l6
! DRAM SELECT LOW ORDER ADDRESS BITS
setx 0x8400000000, %l5, %l6
! DRAM SINGLE CHANNEL MODE
setx 0x8400000000, %l5, %l6
setx 0x8400000000, %l5, %l6
setx 0x8400000000, %l5, %l6
setx 0x8400000000, %l5, %l6
setx 0x8400000000, %l5, %l6
! FBD FAST RESET FLAG (Bug filed 117094)
! Wait for JC to update the Riesling 6/22/06
! setx 0x8400000000, %l5, %l6
setx 0x8400000000, %l5, %l6
! TS1 SOUTHBOUND TO NORTHBOUND MAPPING
setx 0x8400000000, %l5, %l6
setx 0x8400000000, %l5, %l6
! TS3 FAILOVER CONFIGURATION
setx 0x8400000000, %l5, %l6
/************************************************************************
************************************************************************/