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* OpenSPARC T2 Processor File: tcu_regs_peu.s
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* ========== Copyright Header End ============================================
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO
#define TEST_DATA0 0x4c3fdead4c3fbeef
/************************************************************************
************************************************************************/
#define RESET_VEC 0x0000000000000000
#define RESET_VEC 0xfffffffff0000000
SECTION .RED_SEC TEXT_VA = RESET_VEC
setx 0x8800680000, %l5, %l6
! PEU Ingress Credits Initial
setx 0x10000200c0, tmp1, tmp2
setx 0x8800680000, %l5, %l6
! PEU Other Event Log Enable
setx 0x8800681000, %l5, %l6
! PEU Other Event Status Clear
setx 0x8800681000, %l5, %l6
! PEU Other Event Status Set
setx 0x8800681000, %l5, %l6
! PEU Uncorrectable Error Log Enable
setx 0x8800691000, %l5, %l6
! PEU Uncorrectable Error Status Clear
setx 0x8800691000, %l5, %l6
! PEU Uncorrectable Error Status Set
setx 0x8800691000, %l5, %l6
! PEU Receive Uncorrectable Error Header1 Log
setx 0x8800691000, %l5, %l6
! PEU Receive Uncorrectable Error Header2 Log
setx 0x8800691000, %l5, %l6
! PEU Correctable Error Log Enable
setx 0x88006a1000, %l5, %l6
! PEU Correctable Error Status Clear
setx 0x88006a1000, %l5, %l6
! PEU Correctable Error Status Set
setx 0x88006a1000, %l5, %l6
! PEU DLPL/SERDES Revision
setx 0x88006e2000, %l5, %l6
! PEU DLPL Event/Errog Log Enable
setx 0x88006e2000, %l5, %l6
! PEU Serdes PLL Control/Status
setx 0x88006e2000, %l5, %l6
! PEU Serdes Receiver Lane 0 - 7 Control
setx 0x88006e2000, %l5, %l6
! PEU Serdes Transimitter Lane 0 - 7 Status
setx 0x88006e2000, %l5, %l6
! PEU Serdes Macro 0 - 1 Test Configuration
setx 0x88006e2000, %l5, %l6
/************************************************************************
************************************************************************/