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* OpenSPARC T2 Processor File: Debug_Event_L2Odd.s
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* ========== Copyright Header End ============================================
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO
#define Soc_Decr_Pa 0x8600000010
#define Soc_Decr_Val 0x00000000030000
#define L2_ERR_STAT_REG 0xAB00000000
#define L2_ERR_ADDR_REG 0xAC00000000
#define TEST_DATA0 0x1000100081c3e008
#define TEST_DATA1 0x2000200081c3e008
#define TEST_DATA2 0x3000300081c3e008
#define L2_ES_W1C_VALUE 0xc03ffff800000000
#define DRAM_ES_W1C_VALUE 0xfe00000000000000
#define L2_BANK_ADDR 0x40
#define MCU_BANK_ADDR 0x0
#define DRAM_ERR_INJ_REG 0x8400000290
#define DRAM_ERR_STAT_REG 0x8400000280
#define ERROR_ADDR 0x20200000
#define DBG_ERR_PA 0xAA00000040
#define L2_BANK_ADDR 0xc0
#define MCU_BANK_ADDR 0x80
#define DRAM_ERR_INJ_REG 0x8400001290
#define DRAM_ERR_STAT_REG 0x8400001280
#define DBG_ERR_PA 0xAA000000c0
#define L2_BANK_ADDR 0x140
#define MCU_BANK_ADDR 0x100
#define DRAM_ERR_INJ_REG 0x8400002290
#define DRAM_ERR_STAT_REG 0x8400002280
#define ERROR_ADDR 0x20200100
#define DBG_ERR_PA 0xAA00000140
#define L2_BANK_ADDR 0x1c0
#define MCU_BANK_ADDR 0x180
#define DRAM_ERR_INJ_REG 0x8400003290
#define DRAM_ERR_STAT_REG 0x8400003280
#define DBG_ERR_PA 0xAA000001c0
.global My_Corrected_ECC_error_trap
setx Soc_Decr_Val,%l7,%g5
ldxa [%g0] ASI_LSU_CONTROL, %l0
! Remove the lower 2 bits (I-Cache and D-Cache enables)
stxa %l0, [%g0] ASI_LSU_CONTROL
! Clear DRAM Error status register (Bit[63:57] write-1-clear)
setx DRAM_ES_W1C_VALUE, %l0, %l5
setx DRAM_ERR_STAT_REG, %l3, %g5
! add %g5, MCU_BANK_ADDR, %g5
set_DRAM_error_inject_ch0:
mov 0x606, %l1 ! ECC Mask (Multi-bit error)
sllx %l2, DRAM_EI_SSHOT, %l3
Or %l1, %l3, %l1 ! Set single shot ;
sllx %l2, DRAM_EI_ENB, %l3
or %l1, %l3, %l1 ! Enable error injection for the next write
setx DRAM_ERR_INJ_REG, %l3, %g6
! add %g6, MCU_BANK_ADDR, %g6
add %l1, L2_BANK_ADDR, %l1
! Write 1 to clear L2 Error status registers
add %l4, L2_BANK_ADDR, %l4
add %g1, L2_BANK_ADDR, %g1
setx 0x2200aa00, %l0, %g2 ! bits [21:18] select way
add %g2, L2_BANK_ADDR, %g2
! Storing to same L2 way0 but different tag,this will write to mcu
setx 0x2100aa00, %l0, %g3 ! bits [21:18] select way
add %g3, L2_BANK_ADDR, %g3
setx DRAM_ERR_STAT_REG, %l3, %g5
! add %g5, MCU_BANK_ADDR, %g5
setx 0xffc0000000000000, %l0,%o2
sllx %l1, DRAM_ES_DAU, %l0
setx L2_ERR_STAT_REG, %l3, %g5
add %g5, L2_BANK_ADDR, %g5
setx 0xfffffffff0000000, %l3, %l0
andcc %l0, %l6, %l0 ! Donot check L2ESR SYND bits
add %l3, L2_BANK_ADDR, %l3
! Error address is the physical address of the cache line (PA[5:0] 0)
setx 0x2200aa00, %l0, %g2 ! bits [21:18] select way
add %g2, L2_BANK_ADDR, %g2
setx 0xffffffffc0, %l0,%o2
! Check if a Corrected ECC Error Trap happened
mov TT_Data_Access_Error, %l0
My_Corrected_ECC_error_trap:
!My_Recoverable_Sw_error_trap:
/*******************************************************
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