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* OpenSPARC T2 Processor File: fp_pstate_fpdis_n2.s
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#define ENABLE_T0_Fp_disabled_0x20
#define MAIN_PAGE_HV_ALSO
#define MAIN_PAGE_NUCLEUS_ALSO
#define ENABLE_T0_Clean_Window_0x24
#define ENABLE_T0_Corrected_ECC_error_0x63
#define ENABLE_T0_Data_Access_Exception_0x30
#define ENABLE_T0_Data_access_error_0x32
#define ENABLE_T0_Division_By_Zero_0x28
#define ENABLE_T0_Fp_disabled_0x20
#define ENABLE_T0_Fp_exception_ieee_754_0x21
#define ENABLE_T0_Fp_exception_other_0x22
#define ENABLE_HT0_Illegal_instruction_0x10
#define ENABLE_T0_Instruction_Access_MMU_Miss_0x09
#define ENABLE_T0_Instruction_access_error_0x0a
#define ENABLE_T0_Instruction_access_exception_0x08
#define ENABLE_T0_Lddf_Mem_Address_Not_Aligned_0x35
#define ENABLE_T0_Mem_Address_Not_Aligned_0x34
#define ENABLE_T0_Privileged_Action_0x37
#define ENABLE_T0_Privileged_opcode_0x11
#define ENABLE_T0_Stdf_Mem_Address_Not_Aligned_0x36
#define ENABLE_T0_Tag_Overflow_0x23
#define ENABLE_T0_Unimplemented_LDD_0x12
#define ENABLE_T0_Unimplemented_STD_0x13
#define ENABLE_T0_data_access_protection_0x6c
#define ENABLE_T0_fast_data_access_MMU_miss_0x68
#define ENABLE_T0_fast_instr_access_MMU_miss_0x64
.global sam_fast_immu_miss
.global sam_fast_dmmu_miss
**********************************************************
* This diag tests all fp instructions with pstate.pef=0
**********************************************************
wr %g0, 0x7, %fprs /* make sure fef is 1 */
mov 0xfef, %l1 /* set pstate.pef[4] to 0 */
********************************
********************************
/* Expect every fp instruction to be faulted
Set a count in %l7, this is incremented in the trap handler.
Read PC at the end into %l6
%l4 is for incrementing illegal instruction trap count
%l3 is for incrementing illegal instruction expected trap count
wr %g0, 0x0, %asi ! Set it to 0 - this should be irrelevant
fbn test_fail ! This is not causing trap (??)
fbn,pt %fcc0, test_fail ! This is not cauing trap (??)
fbuge,pt %fcc0, test_fail
fbule,pt %fcc0, test_fail
/* floating point add and subtract */
/* floating point add and subtract */
/* Floating point multiply and divide */
/* Floating point square root */
/* Load Floating point */
add %l3, 0x1, %l3 ! Expect illegal inst. trap
ldq [%g0], %f0 ! This is causing 0x10 (??)
add %l3, 0x1, %l3 ! Expect illegal inst. trap
.word 0xc5080000 ! %fsr p. 174 - (op3=0x21, rd = 2..31) - rd = 0x2
add %l3, 0x1, %l3 ! Expect illegal inst. trap
.word 0xff080000 ! %fsr p. 174 - (op3=0x21, rd = 2..31) - rd = 0x31
/* Load Floating point asi */
add %l3, 0x1, %l3 ! Expect illegal inst. trap
add %l3, 0x1, %l3 ! Expect illegal inst. trap
/* Floating point move on %icc or %xcc */
/* Floating point move on integer register */
.word 0x8da85ce0 ! Should cause fp exception other for quads but fp disabled is higher prio
.word 0x89a840e0 ! Should cause fp exception other (rcond=000) but fp disabled is higher pri (??)
.word 0x89a850e0 ! Should cause fp exception other (rcond=100) but fp disabled is higher pri (??)
/* Integer move on floating point CC */
add %l3, 0x1, %l3 ! Expect illegal inst. trap
rdpr %fq, %g0 ! illegal instruction (??)
rd %fprs, %g0 ! This shouldnt cause a trap
/* Floating point store */
add %l3, 0x1, %l3 ! Expect illegal inst. trap
add %l3, 0x1, %l3 ! Expect illegal inst. trap
.word 0xc5280000 ! %fsr p. 226 - (op3=0x25, rd = 2..31) - rd = 0x2
add %l3, 0x1, %l3 ! Expect illegal inst. trap
.word 0xfd280000 ! %fsr p. 226 - (op3=0x25, rd = 2..31) - rd = 0x31
/* Floating point store asi */
add %l3, 0x1, %l3 ! Expect illegal inst. trap
add %l3, 0x1, %l3 ! Expect illegal inst. trap
wr %g0, 0x0, %fprs ! This shouldnt cause a trap
/* Branch to test done - self checking - Cant trust SIMICS entirely */
rd %pc, %l6 ! read pc and save it
subcc %l3, %l4, %l2 ! Check illegal inst. trap count
! bne test_fail if illegal inst. trap count doesnt match, test failed
sub %l6, %l5, %l5 ! Subtract both PCs
srl %l5, 0x2, %l5 ! Get the count
sub %l5, %l3, %l5 ! Account for add instructions
sub %l5, 0x1, %l5 ! Account for rd pc operations
! bne test_fail ! if the total trap count doesnt match, test failed