* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: interrupt0x60_handler.s.pal
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
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* ========== Copyright Header End ============================================
# $Id: interrupt0x60_handler.s.pal,v 1.14 2006/12/01 19:20:42 granvold Exp $
$hw_num_ivs = 64; $hw_max_ivn = $hw_num_ivs - 1;
$hw_num_threads = 64; $hw_max_thread_num = $hw_num_threads - 1;
# interrupt0x60 constraints:
$max_cc_ivns = 48; $max_cc_ivns_m1 = $max_cc_ivns - 1;
$max_niu_ivns = 16; $max_niu_ivns_m1 = $max_niu_ivns - 1;
$max_msi_idx = 8; $max_msi_idx_m1 = $max_msi_idx - 1;
/* Shared trap handler for interrupts (TT=0x60) */
/*>>>>>> ONLY EDIT THE .pal VERSION OF THIS FILE <<<<<<<<*/
* This is tightly linked with interrupt0x60_defines.h and
* interrupt0x60_sys_init.s
* There are several different consumers of interrupt information:
* 1. random test generators which stimulate interrupts
* 2. boot code that initializes interrupt-related registers
* 3. the shared interrupt trap handler
#include "bobo_defines.h"
mov %g7, %o7 ! Restore %o7
ldxa [%g0] ASI_INTR_ID, %g1 ! Get the thread number
ldxa [%g0] ASI_INTR_R, %g2 ! Get the interrupt vector number
setx intr0x60_ivn_to_ig, %g4, %g3
#ifdef INTR0x60_NIU_TX_IV_0
cmp %g4, INTR0x60_IG_NIU_TX
be intr0x60_handle_niu_tx
#endif /* INTR0x60_NIU_TX_IV_0 */
#ifdef INTR0x60_NIU_RX_IV_0
cmp %g4, INTR0x60_IG_NIU_RX
be intr0x60_handle_niu_rx
#endif /* INTR0x60_NIU_RX_IV_0 */
#endif /* INTR0x60_MONDO_IV */
#if (INTR0x60_SSI_ERR_IV != INTR0x60_BAD_IV)
cmp %g4, INTR0x60_IG_SSI_ERR
be intr0x60_handle_ssi_err
#endif /* (INTR0x60_SSI_ERR_IV != INTR0x60_BAD_IV) */
#if (INTR0x60_SSI_INT_IV != INTR0x60_BAD_IV)
cmp %g4, INTR0x60_IG_SSI_INT
be intr0x60_handle_ssi_int
#endif /* (INTR0x60_SSI_INT_IV != INTR0x60_BAD_IV) */
/* If we get here, we got an unexpected vector number */
!\$EV trig_pc_d(1, \@VA(.HTRAPS.intr0x60_bad_ivn)) -> printf("ERROR: Bad interrupt vector number",*,1)
/************************************************************************/
/* Handle cross-call interrupts */
!\$EV trig_pc_d(1, \@VA(.HTRAPS.intr0x60_handle_cc)) -> printf("INFO: Cross-call interrupt received",*,1)
#ifndef INTR0x60_CC_DEST_ALL
/* Make sure that this thread is allowed to receive cross-calls */
setx intr0x60_handle_cc_thread_table, %g5, %g4
brz %g4, intr0x60_handle_cc_bad_thread
#endif /* INTR0x60_CC_DEST_ALL */
/* Include any extra cross-call handler from the user */
/* The code can assume that %g1 is the thread and %g2 is the vector */
#ifdef INTR0x60_CC_EXTRA_HANDLER
intr0x60_handle_cc_extra_handler:
INTR0x60_CC_EXTRA_HANDLER
#endif /* INTR0x60_CC_EXTRA_HANDLER */
intr0x60_handle_cc_retry:
/* Retry the instruction that was trapped */
#ifndef INTR0x60_CC_DEST_ALL
intr0x60_handle_cc_bad_thread:
!\$EV trig_pc_d(1, \@VA(.HTRAPS.intr0x60_handle_cc_bad_thread)) -> printf("ERROR: Cross-call received on unexpected thread",*,1)
intr0x60_handle_cc_thread_table:
>for ($thread = 0; $thread < $hw_num_threads; $thread++) {
#if defined(INTR0x60_CC_DEST_${thread})
#endif /* INTR0x60_CC_DEST_ALL */
#ifdef INTR0x60_NIU_TX_IV_0
/************************************************************************/
/* Handle NIU TX interrupts */
!\$EV trig_pc_d(1, \@VA(.HTRAPS.intr0x60_handle_niu_tx)) -> printf("INFO: NIU TX interrupt received",*,1)
/* Make sure that this thread is the right one for this NIU interrupt */
>for ($ivn = 0; $ivn < $max_niu_ivns; $ivn++) {
#ifdef INTR0x60_NIU_TX_IV_${ivn}
intr0x60_handle_niu_tx_check_thread_${ivn}:
cmp %g2, INTR0x60_NIU_TX_IV_${ivn}
cmp %g7, INTR0x60_NIU_TX_THREAD_${ivn}
cmp %g1, INTR0x60_NIU_TX_THREAD_${ivn}
bnz intr0x60_handle_niu_tx_bad_thread
best_set_reg(INTR0x60_NIU_TX_DMA_${ivn}, %g7, %g3)
ba intr0x60_handle_niu_tx_good_thread
#endif /* INTR0x60_NIU_TX_IV_${ivn} */
/* If we get here, we have an unknown vector */
intr0x60_handle_niu_tx_bad_vector:
!\$EV trig_pc_d(1, \@VA(.HTRAPS.intr0x60_handle_niu_tx_bad_vector)) -> printf("interrupt0x60_handler.s ERROR: intr0x60_iv_to_ig said this is an NIU TX interrupt, but it is not defined in INTR0x60_NIU_TX_IV_x",*,1)
/* If we get here, we know we have the right thread for this vector */
intr0x60_handle_niu_tx_good_thread:
/* Clear the source of the interrupt */
! Re-enable the interrupt in the transmit DMA channel
best_set_reg(TX_CS, %g7, %g4) ! TX_CS
best_set_reg(TDMC_STEP, %g7, %g5)
mulx %g5, %g3, %g5 ! %g3 is the DMA TX channel
ldxa [%g4]ASI_PRIMARY_LITTLE, %g0 ! Reset MK
! Re-enable the interrupt in the NIU
best_set_reg(LDGIMGN, %g7, %g4) ! LDGIMGN
best_set_reg(LDGIMGN_STEP, %g7, %g5)
best_set_reg(0x80000001, %g7, %g5)
stxa %g5, [%g4]ASI_PRIMARY_LITTLE
/* Include any extra NIU handler from the user */
/* The code can assume that %g1 is the thread, %g2 is the vector,
* and %g3 is the TX DMA channel */
#ifdef INTR0x60_NIU_TX_EXTRA_HANDLER
intr0x60_handle_niu_tx_extra_handler:
INTR0x60_NIU_TX_EXTRA_HANDLER
#endif /* INTR0x60_NIU_TX_EXTRA_HANDLER */
intr0x60_handle_niu_tx_retry:
/* Retry the instruction that was trapped */
intr0x60_handle_niu_tx_bad_thread:
!\$EV trig_pc_d(1, \@VA(.HTRAPS.intr0x60_handle_niu_tx_bad_thread)) -> printf("ERROR: NIU TX interrupt received on unexpected thread",*,1)
#endif /* INTR0x60_NIU_TX_IV_0 */
#ifdef INTR0x60_NIU_RX_IV_0
/************************************************************************/
/* Handle NIU RX interrupts */
!\$EV trig_pc_d(1, \@VA(.HTRAPS.intr0x60_handle_niu_rx)) -> printf("INFO: NIU RX interrupt received",*,1)
/* Make sure that this thread is the right one for this NIU interrupt */
>for ($ivn = 0; $ivn < $max_niu_ivns; $ivn++) {
#ifdef INTR0x60_NIU_RX_IV_${ivn}
intr0x60_handle_niu_rx_check_thread_${ivn}:
cmp %g2, INTR0x60_NIU_RX_IV_${ivn}
cmp %g7, INTR0x60_NIU_RX_THREAD_${ivn}
cmp %g1, INTR0x60_NIU_RX_THREAD_${ivn}
bnz intr0x60_handle_niu_rx_bad_thread
best_set_reg(INTR0x60_NIU_RX_DMA_${ivn}, %g7, %g3)
ba intr0x60_handle_niu_rx_good_thread
#endif /* INTR0x60_NIU_RX_IV_${ivn} */
/* If we get here, we have an unknown vector */
intr0x60_handle_niu_rx_bad_vector:
!\$EV trig_pc_d(1, \@VA(.HTRAPS.intr0x60_handle_niu_rx_bad_vector)) -> printf("interrupt0x60_handler.s ERROR: intr0x60_iv_to_ig said this is an NIU RX interrupt, but it is not defined in INTR0x60_NIU_RX_IV_x",*,1)
/* If we get here, we know we have the right thread for this vector */
intr0x60_handle_niu_rx_good_thread:
/* Clear the source of the interrupt */
best_set_reg(RX_DMA_CTL_STAT, %g7, %g4)
mulx %g3, RX_DMA_CTL_STAT_STEP, %g7 ! %g3 is the DMA RX channel
add %g4, %g7, %g4 ! Addr of RX DMA Ctl/stat for this channel
intr0x60_handle_niu_rx_get_rx_dma_ctl_stat:
ldxa [%g4]ASI_PRIMARY_LITTLE, %g5 ! Get status
sllx %g7, 32, %g7 ! Mask for clear-on-reset error bits
brz %g7, intr0x60_handle_niu_rx_nonfatal
intr0x60_handle_niu_rx_fatal_error:
#ifdef INTR0x60_NIU_RX_FATAL_HANDLER
INTR0x60_NIU_RX_FATAL_HANDLER
#else /* INTR0x60_NIU_RX_FATAL_HANDLER */
#ifdef INTR0x60_NIU_RX_CLEAR_FATAL_FOR_TSOTOOL
/* This code does what is needed for tsotool NIU RX fatal error interrupts */
best_set_reg(RXDMA_CFIG1, %g7, %g4)
mulx %g3, RX_DMA_CTL_STAT_STEP, %g7 ! %g3 is the DMA RX channel
intr0x60_handle_niu_rx_fatal_error_disable_dma_channel:
stxa %g0, [%g4]ASI_PRIMARY_LITTLE
sllx %g7, 30, %g7 ! RST bit in RXDMA_CFIG1
intr0x60_handle_niu_rx_fatal_error_reset_dma_channel:
stxa %g7, [%g4]ASI_PRIMARY_LITTLE
srlx %g7, 1, %g7 ! QST bit in RXDMA_CFIG1
intr0x60_handle_niu_rx_fatal_error_wait_for_dma_channel:
ldxa [%g4]ASI_PRIMARY_LITTLE, %g5 ! Get the status
beq intr0x60_handle_niu_rx_fatal_error_enable_intr_for_dma_channel
brnz %g6, intr0x60_handle_niu_rx_fatal_error_wait_for_dma_channel
intr0x60_handle_niu_rx_fatal_error_timeout_wait_for_dma_channel:
!\$EV trig_pc_d(1, \@VA(.HTRAPS.intr0x60_handle_niu_rx_fatal_error_timeout_wait_for_dma_channel)) -> printf("ERROR: NIU RX interrupt received for fatal error and DMA channel reset never completed",*,1)
intr0x60_handle_niu_rx_fatal_error_enable_intr_for_dma_channel:
best_set_reg(RX_DMA_ENT_MSK, %g7, %g5)
mulx %g3, RX_DMA_CTL_STAT_STEP, %g7 ! %g3 is the DMA RX channel
stxa %g0, [%g5]ASI_PRIMARY_LITTLE
ba intr0x60_handle_niu_rx_reenable_ldg
#else /* INTR0x60_NIU_RX_CLEAR_FATAL_FOR_TSOTOOL */
!\$EV trig_pc_d(1, \@VA(.HTRAPS.intr0x60_handle_niu_rx_fatal_error)) -> printf("ERROR: NIU RX interrupt received for fatal error",*,1)
#endif /* INTR0x60_NIU_RX_CLEAR_FATAL_FOR_TSOTOOL */
#endif /* INTR0x60_NIU_RX_FATAL_HANDLER */
intr0x60_handle_niu_rx_nonfatal:
best_set_reg(0xffffffffffff0000, %g7, %g6)
and %g5, %g6, %g5 ! Only preserve error bits, for RW1C
best_set_reg(RCR_STAT_A, %g7, %g6)
mulx %g3, RX_DMA_CTL_STAT_STEP, %g7 ! %g3 is the DMA RX channel
intr0x60_handle_niu_rx_get_rcr_stat_a:
ldxa [%g6]ASI_PRIMARY_LITTLE, %g6 ! Get the number of pkts received
best_set_reg(THRES_INT, %g7, %g5) ! Bit to enable mailbox (MEX in PRM)
intr0x60_handle_niu_rx_reset_rx_dma_ctl_stat:
stxa %g6, [%g4]ASI_PRIMARY_LITTLE ! RW1C on RCRTHRES, RCRTO, etc., plus
! set MEX, decrement QLEN by pkt read
intr0x60_handle_niu_rx_reenable_ldg:
! Re-enable the interrupt in the NIU LDG
best_set_reg(LDGIMGN, %g7, %g4) ! LDGIMGN
best_set_reg(LDGIMGN_STEP, %g7, %g5)
best_set_reg(0x80000001, %g7, %g5)
stxa %g5, [%g4]ASI_PRIMARY_LITTLE ! Arm LDGI, set timer to 1
/* Include any extra NIU handler from the user */
/* The code can assume that %g1 is the thread, %g2 is the vector,
* and %g3 is the RX DMA channel */
#ifdef INTR0x60_NIU_RX_EXTRA_HANDLER
intr0x60_handle_niu_rx_extra_handler:
INTR0x60_NIU_RX_EXTRA_HANDLER
#endif /* INTR0x60_NIU_RX_EXTRA_HANDLER */
intr0x60_handle_niu_rx_retry:
/* Retry the instruction that was trapped */
intr0x60_handle_niu_rx_bad_thread:
!\$EV trig_pc_d(1, \@VA(.HTRAPS.intr0x60_handle_niu_rx_bad_thread)) -> printf("ERROR: NIU RX interrupt received on unexpected thread",*,1)
#endif /* INTR0x60_NIU_RX_IV_0 */
/************************************************************************/
/* Handle PIU interrupts */
!\$EV trig_pc_d(1, \@VA(.HTRAPS.intr0x60_handle_piu)) -> printf("INFO: PIU interrupt received",*,1)
#ifndef INTR0x60_DO_NOT_READ_ADATA1
/* To reach coverage goals, do a dummy read from ADATA1 */
best_set_reg(MONDO_INT_ADATA1, %g4, %g3)
#endif /* INTR0x60_DO_NOT_READ_ADATA1 */
best_set_reg(MONDO_INT_ADATA0, %g4, %g3)
and %g3, 0x3f, %g3 /* WIP: Mask to get INO */
be intr0x60_handle_piu_inta
#endif /* INTR0x60_MONDO_20_V */
be intr0x60_handle_piu_intb
#endif /* INTR0x60_MONDO_21_V */
be intr0x60_handle_piu_intc
#endif /* INTR0x60_MONDO_22_V */
be intr0x60_handle_piu_intd
#endif /* INTR0x60_MONDO_23_V */
>for $idx (0 .. $max_msi_idx_m1) {
#ifdef INTR0x60_MSI_${idx}_NUM
intr0x60_handle_piu_check_msi_${idx}:
cmp %g3, mpeval(INTR0x60_MSI_${idx}_EQN+24)
be intr0x60_handle_piu_msi_${idx}
#endif /* INTR0x60_MSI_${idx}_NUM */
#ifdef INTR0x60_PM_PME_EQN
intr0x60_handle_piu_check_pm_pme:
cmp %g3, mpeval(INTR0x60_PM_PME_EQN+24)
be intr0x60_handle_piu_pm_pme
#endif /* INTR0x60_PM_PME_EQN */
#ifdef INTR0x60_PME_TO_ACK_EQN
intr0x60_handle_piu_check_pme_to_ack:
cmp %g3, mpeval(INTR0x60_PME_TO_ACK_EQN+24)
be intr0x60_handle_piu_pme_to_ack
#endif /* INTR0x60_PME_TO_ACK_EQN */
/* If we get here, we got an unexpected INO */
!\$EV trig_pc_d(1, \@VA(.HTRAPS.intr0x60_bad_mondo_INO)) -> printf("ERROR: Bad mondo INO",*,1)
>@intx_letters = ("A", "B", "C", "D");
>for ($intx = 0; $intx < 4; $intx++) {
> $uc = $intx_letters[$intx];
#if INTR0x60_MONDO_${ino}_V
/************ Handle INT${uc} ***********/
intr0x60_handle_piu_int${lc}:
/* Check whether this thread matches this INO */
cmp %g7/*tid*/, INTR0x60_MONDO_${ino}_THREAD
cmp %g1/*tid*/, INTR0x60_MONDO_${ino}_THREAD
bne intr0x60_handle_piu_bad_thread
/* Clear the interrupt */
intr0x60_handle_piu_int${lc}_deassert:
! Offset accesses by PCIE_MEM64_OFFSET since
! BAR is set that way. Physical addresses generated via TSB
! have this offset so mimic that when accessing directly, as here.
best_set_reg(mpeval(N2_PCIE_BASE_ADDR
+ MEM64_OFFSET_BASE_REG_DATA
+ BOBO_INTR_VECT_STATUS_OFFSET), %g7, %g4)
mov eval(1 << $intx), %g5
! Offset accesses by PCIE_MEM64_OFFSET since
! BAR is set that way. Physical addresses generated via TSB
! have this offset so mimic that when accessing directly, as here.
best_set_reg(mpeval(N2_PCIE_BASE_ADDR
+ MEM64_OFFSET_BASE_REG_DATA
+ (INTR0x60_MONDO_${ino}_DMAEPT_ENGINE << 8)
+ DMAEPT_INTERRUPT_ACK), %g7, %g4)
best_set_reg(DMAEPT_INTERRUPT_ACK_INT${uc}, %g7, %g5)
#else /* FC_NO_PEU_VERA */
! \$EV trig_pc_d(1, \@VA(.HTRAPS.intr0x60_handle_piu_int${lc}_deassert)) -> EnablePCIeIgCmd ("INT${uc}", 0, 0, "DEASSERT", 1, *, 1 )
#endif /* FC_NO_PEU_VERA */
/* Loop on the INTX Status Register until the deassert message
* has arrived and been processed. */
best_set_reg(PCI_E_INTX_STATUS_ADDR, %g5, %g4)
best_set_reg(INTR0x60_INTX_DEASSERT_TIMEOUT, %g5, %g6)
intr0x60_handle_piu_int${lc}_deassert_loop:
brz %g6, intr0x60_handle_piu_int${lc}_deassert_timeout
and %g3, ${bit}, %g3 ! ${bit} == bit for INT${uc}
brnz %g3, intr0x60_handle_piu_int${lc}_deassert_loop
intr0x60_handle_piu_int${lc}_clear:
best_set_reg(PCI_E_INT_${uc}_CLEAR_ADDR, %g5, %g4)
best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR+${intx}*PCI_E_INT_CLEAR_STEP), %g5, %g4)
best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
/* Include any extra INT${uc} handler from the user */
/* The code can assume that %g1 is the thread and %g2 is the vector */
#ifdef INTR0x60_INT${uc}_EXTRA_HANDLER
intr0x60_handle_int${lc}_extra_handler:
INTR0x60_INT${uc}_EXTRA_HANDLER
#endif /* INTR0x60_INT${uc}_EXTRA_HANDLER */
intr0x60_handle_piu_int${lc}_retry:
/* Retry the instruction that was trapped */
#endif /* INTR0x60_MONDO_${ino}_V */
/* If we get here, the interrupt status bit didn't deassert */
intr0x60_handle_piu_int${lc}_deassert_timeout:
!\$EV trig_pc_d(1, \@VA(.HTRAPS.intr0x60_handle_piu_int${lc}_deassert_timeout)) -> printf("ERROR: INT${uc} status bit did not deassert within INTR0x60_INTX_DEASSERT_TIMEOUT iterations",*,1)
>for $idx (0 .. $max_msi_idx_m1) {
#ifdef INTR0x60_MSI_${idx}_NUM
/************ Handle MSI ${idx} ***********/
intr0x60_handle_piu_msi_${idx}:
!WIP: /* Check whether this thread matches this INO */
!WIP: cmp %g1/*tid*/, INTR0x60_MONDO_XXX_THREAD
!WIP: bne intr0x60_handle_piu_bad_thread
/* Clear the interrupt */
intr0x60_handle_piu_msi_${idx}_clear_eqwr:
sllx %g4, 62, %g4 ! EQWR_N is bit 62
best_set_reg(mpeval(PCI_E_MSI_CLEAR_ADDR
+PCI_E_MSI_CLEAR_STEP*INTR0x60_MSI_${idx}_NUM),
stx %g4, [%g5] ! clear EQWR in MSI map reg.
intr0x60_handle_piu_msi_${idx}_disable_eq:
sllx %g4, 44, %g4 ! DIS is bit 44
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_CLEAR_ADDR
+PCI_E_EV_QUE_CTL_CLEAR_STEP*INTR0x60_MSI_${idx}_EQN),
! Set Event Queue Head = Event Queue Tail
intr0x60_handle_piu_msi_${idx}_reset_eq_head:
best_set_reg(mpeval(PCI_E_EV_QUE_TAIL_ADDR
+PCI_E_EV_QUE_TAIL_STEP*INTR0x60_MSI_${idx}_EQN),
best_set_reg(mpeval(PCI_E_EV_QUE_HEAD_ADDR
+PCI_E_EV_QUE_HEAD_STEP*INTR0x60_MSI_${idx}_EQN),
intr0x60_handle_piu_msi_${idx}_clear_int:
best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR
+(4+INTR0x60_MSI_${idx}_EQN)*PCI_E_INT_CLEAR_STEP),
/* Include any extra MSI handler from the user that needs to be
* executed while the mondo busy flag is still asserted. */
/* The code can assume that %g1 is the thread,
#ifdef INTR0x60_MSI_${idx}_EXTRA_HANDLER_WHILE_BUSY
intr0x60_handle_msi_${idx}_extra_handler_while_busy:
INTR0x60_MSI_${idx}_EXTRA_HANDLER_WHILE_BUSY
#endif /* INTR0x60_MSI_${idx}_EXTRA_HANDLER_WHILE_BUSY */
intr0x60_handle_piu_msi_${idx}_clear_mondo_busy:
best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
/* Include any extra MSI handler from the user that needs to be
* executed while the event queue is disabled. */
/* The code can assume that %g1 is the thread,
#ifdef INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
intr0x60_handle_msi_extra_handler_while_eq_disabled_${idx}:
INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED
#endif /* INTR0x60_MSI_EXTRA_HANDLER_WHILE_EQ_DISABLED */
intr0x60_handle_piu_msi_${idx}_enable_eq:
sllx %g4, 44, %g4 ! EN is bit 44
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_ADDR
+PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_MSI_${idx}_EQN),
ba intr0x60_handle_msi_extra_handler
#endif /* INTR0x60_MSI_${idx}_NUM */
/* Include any extra MSI handler from the user */
/* The code can assume that %g1 is the thread,
intr0x60_handle_msi_extra_handler:
#ifdef INTR0x60_MSI_EXTRA_HANDLER
INTR0x60_MSI_EXTRA_HANDLER
#endif /* INTR0x60_MSI_EXTRA_HANDLER */
intr0x60_handle_piu_msi_retry:
/* Retry the instruction that was trapped */
#ifdef INTR0x60_PM_PME_EQN
/************ Handle PM_PME ***********/
intr0x60_handle_piu_pm_pme:
!WIP: /* Check whether this thread matches this INO */
!WIP: cmp %g1/*tid*/, INTR0x60_MONDO_XXX_THREAD
!WIP: bne intr0x60_handle_piu_bad_thread
/* Clear the interrupt */
intr0x60_handle_piu_pm_pme_disable_eq:
sllx %g4, 44, %g4 ! DIS is bit 44
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_CLEAR_ADDR
+PCI_E_EV_QUE_CTL_CLEAR_STEP*INTR0x60_PM_PME_EQN),
! Set Event Queue Head = Event Queue Tail
intr0x60_handle_piu_pm_pme_reset_eq_head:
best_set_reg(mpeval(PCI_E_EV_QUE_TAIL_ADDR
+PCI_E_EV_QUE_TAIL_STEP*INTR0x60_PM_PME_EQN),
best_set_reg(mpeval(PCI_E_EV_QUE_HEAD_ADDR
+PCI_E_EV_QUE_HEAD_STEP*INTR0x60_PM_PME_EQN),
intr0x60_handle_piu_pm_pme_clear_int:
best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR
+(4+INTR0x60_PM_PME_EQN)*PCI_E_INT_CLEAR_STEP),
intr0x60_handle_piu_pm_pme_clear_mondo_busy:
best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
/* Include any extra PM_PME handler from the user that needs to be
* executed while the event queue is disabled. */
/* The code can assume that %g1 is the thread,
#ifdef INTR0x60_PM_PME_EXTRA_HANDLER_WHILE_EQ_DISABLED
intr0x60_handle_pm_pme_extra_handler_while_eq_disabled:
INTR0x60_PM_PME_EXTRA_HANDLER_WHILE_EQ_DISABLED
#endif /* INTR0x60_PM_PME_EXTRA_HANDLER_WHILE_EQ_DISABLED */
intr0x60_handle_piu_pm_pme_enable_eq:
sllx %g4, 44, %g4 ! EN is bit 44
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_ADDR
+PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_PM_PME_EQN),
/* Include any extra PM_PME handler from the user */
/* The code can assume that %g1 is the thread,
intr0x60_handle_pm_pme_extra_handler:
#ifdef INTR0x60_PM_PME_EXTRA_HANDLER
INTR0x60_PM_PME_EXTRA_HANDLER
#endif /* INTR0x60_PM_PME_EXTRA_HANDLER */
intr0x60_handle_piu_pm_pme_retry:
/* Retry the instruction that was trapped */
#endif /* INTR0x60_PM_PME_EQN */
#ifdef INTR0x60_PME_TO_ACK_EQN
/************ Handle PME_TO_ACK ***********/
intr0x60_handle_piu_pme_to_ack:
!WIP: /* Check whether this thread matches this INO */
!WIP: cmp %g1/*tid*/, INTR0x60_MONDO_XXX_THREAD
!WIP: bne intr0x60_handle_piu_bad_thread
/* Clear the interrupt */
intr0x60_handle_piu_pme_to_ack_disable_eq:
sllx %g4, 44, %g4 ! DIS is bit 44
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_CLEAR_ADDR
+PCI_E_EV_QUE_CTL_CLEAR_STEP*INTR0x60_PME_TO_ACK_EQN),
! Set Event Queue Head = Event Queue Tail
intr0x60_handle_piu_pme_to_ack_reset_eq_head:
best_set_reg(mpeval(PCI_E_EV_QUE_TAIL_ADDR
+PCI_E_EV_QUE_TAIL_STEP*INTR0x60_PME_TO_ACK_EQN),
best_set_reg(mpeval(PCI_E_EV_QUE_HEAD_ADDR
+PCI_E_EV_QUE_HEAD_STEP*INTR0x60_PME_TO_ACK_EQN),
intr0x60_handle_piu_pme_to_ack_clear_int:
best_set_reg(mpeval(PCI_E_INT_CLEAR_ADDR
+(4+INTR0x60_PME_TO_ACK_EQN)*PCI_E_INT_CLEAR_STEP),
intr0x60_handle_piu_pme_to_ack_clear_mondo_busy:
best_set_reg(MONDO_INT_ABUSY, %g5, %g4)
/* Include any extra PME_TO_ACK handler from the user that needs to be
* executed while the event queue is disabled. */
/* The code can assume that %g1 is the thread,
#ifdef INTR0x60_PME_TO_ACK_EXTRA_HANDLER_WHILE_EQ_DISABLED
intr0x60_handle_pme_to_ack_extra_handler_while_eq_disabled:
INTR0x60_PME_TO_ACK_EXTRA_HANDLER_WHILE_EQ_DISABLED
#endif /* INTR0x60_PME_TO_ACK_EXTRA_HANDLER_WHILE_EQ_DISABLED */
intr0x60_handle_piu_pme_to_ack_enable_eq:
sllx %g4, 44, %g4 ! EN is bit 44
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_ADDR
+PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_PME_TO_ACK_EQN),
/* Include any extra PME_TO_ACK handler from the user */
/* The code can assume that %g1 is the thread,
intr0x60_handle_pme_to_ack_extra_handler:
#ifdef INTR0x60_PME_TO_ACK_EXTRA_HANDLER
INTR0x60_PME_TO_ACK_EXTRA_HANDLER
#endif /* INTR0x60_PME_TO_ACK_EXTRA_HANDLER */
intr0x60_handle_piu_pme_to_ack_retry:
/* Retry the instruction that was trapped */
#endif /* INTR0x60_PME_TO_ACK_EQN */
intr0x60_handle_piu_bad_thread:
!\$EV trig_pc_d(1, \@VA(.HTRAPS.intr0x60_handle_piu_bad_thread)) -> printf("ERROR: Mondo delivered to wrong thread",*,1)
#endif /* INTR0x60_MONDO_IV */
#if (INTR0x60_SSI_ERR_IV != INTR0x60_BAD_IV)
/************************************************************************/
/* Handle SSI parity error interrupts */
!\$EV trig_pc_d(1, \@VA(.HTRAPS.intr0x60_handle_ssi_err)) -> printf("INFO: SSI parity error interrupt received",*,1)
/* Make sure that this thread is the right one */
best_set_reg(INTR0x60_SSI_ERR_THREAD, %g7, %g4)
bne intr0x60_handle_ssi_err_bad_thread
/* Include any extra SSI parity error handler from the user */
/* The code can assume that %g1 is the thread and %g2 is the vector */
#ifdef INTR0x60_SSI_ERR_EXTRA_HANDLER
intr0x60_handle_ssi_err_extra_handler:
INTR0x60_SSI_ERR_EXTRA_HANDLER
#endif /* INTR0x60_SSI_ERR_EXTRA_HANDLER */
intr0x60_handle_ssi_err_retry:
/* Retry the instruction that was trapped */
intr0x60_handle_ssi_err_bad_thread:
!\$EV trig_pc_d(1, \@VA(.HTRAPS.intr0x60_handle_ssi_err_bad_thread)) -> printf("ERROR: SSI parity error interrupt received on unexpected thread",*,1)
#endif /* (INTR0x60_SSI_ERR_IV != INTR0x60_BAD_IV) */
#if (INTR0x60_SSI_INT_IV != INTR0x60_BAD_IV)
/************************************************************************/
/* Handle SSI_EXT_INT_L interrupts */
!\$EV trig_pc_d(1, \@VA(.HTRAPS.intr0x60_handle_ssi_int)) -> printf("INFO: SSI_EXT_INT_L interrupt received",*,1)
/* Make sure that this thread is the right one */
best_set_reg(INTR0x60_SSI_INT_THREAD, %g7, %g4)
bne intr0x60_handle_ssi_int_bad_thread
/* Include any extra SSI_EXT_INT_L handler from the user */
/* The code can assume that %g1 is the thread and %g2 is the vector */
#ifdef INTR0x60_SSI_INT_EXTRA_HANDLER
intr0x60_handle_ssi_int_extra_handler:
INTR0x60_SSI_INT_EXTRA_HANDLER
#endif /* INTR0x60_SSI_INT_EXTRA_HANDLER */
intr0x60_handle_ssi_int_retry:
/* Retry the instruction that was trapped */
intr0x60_handle_ssi_int_bad_thread:
!\$EV trig_pc_d(1, \@VA(.HTRAPS.intr0x60_handle_ssi_int_bad_thread)) -> printf("ERROR: SSI_EXT_INT_L interrupt received on unexpected thread",*,1)
#endif /* (INTR0x60_SSI_INT_IV != INTR0x60_BAD_IV) */
* Need to have some tables to identify the source of the interrupt
* and whether it is expected for this thread.
* intr0x60_ivn_to_ig has one byte per interrupt vector number (0-63),
* which indicates the interrupt group, encoded as
>for ($count = 0; $count < $max_cc_ivns; $count++) {
#ifdef INTR0x60_CC_IV_${count}
#define INTR0x60_CC_IV_${count}_CHECK (INTR0x60_CC_IV_${count} == `\$1')
#define INTR0x60_CC_IV_${count}_CHECK (0)
>for ($count = 0; $count < $max_niu_ivns; $count++) {
#ifdef INTR0x60_NIU_RX_IV_${count}
#define INTR0x60_NIU_RX_IV_${count}_CHECK (INTR0x60_NIU_RX_IV_${count} == `\$1')
#define INTR0x60_NIU_RX_IV_${count}_CHECK (0)
>for ($count = 0; $count < $max_niu_ivns; $count++) {
#ifdef INTR0x60_NIU_TX_IV_${count}
#define INTR0x60_NIU_TX_IV_${count}_CHECK (INTR0x60_NIU_TX_IV_${count} == `\$1')
#define INTR0x60_NIU_TX_IV_${count}_CHECK (0)
#if (INTR0x60_SSI_ERR_IV != INTR0x60_BAD_IV)
#define INTR0x60_SSI_ERR_IV_CHECK (INTR0x60_SSI_ERR_IV == `\$1')
#define INTR0x60_SSI_ERR_IV_CHECK (0)
#if (INTR0x60_SSI_INT_IV != INTR0x60_BAD_IV)
#define INTR0x60_SSI_INT_IV_CHECK (INTR0x60_SSI_INT_IV == `\$1')
#define INTR0x60_SSI_INT_IV_CHECK (0)
#define INTR0x60_MONDO_IV_CHECK (INTR0x60_MONDO_IV == `\$1')
#define INTR0x60_MONDO_IV_CHECK (0)
/* Note: Need to put INTR0x60_IG_* names on a separate line
* because the *_CHECK macros may contain a half-quote which
* would prevent cpp from doing the macro replacement */
define(`INTR0x60_IVN_TO_IG',
`ifelse(eval( INTR0x60_CC_IV_0_CHECK
>for ($count = 1; $count < $max_cc_ivns-1; $count++) {
|| INTR0x60_CC_IV_${count}_CHECK
|| INTR0x60_CC_IV_${count}_CHECK), 1,
eval( INTR0x60_SSI_ERR_IV_CHECK ), 1,
eval( INTR0x60_SSI_INT_IV_CHECK ), 1,
eval( INTR0x60_MONDO_IV_CHECK ), 1,
eval( INTR0x60_NIU_RX_IV_0_CHECK
>for ($count = 1; $count < $max_niu_ivns-1; $count++) {
|| INTR0x60_NIU_RX_IV_${count}_CHECK
|| INTR0x60_NIU_RX_IV_${count}_CHECK), 1,
eval( INTR0x60_NIU_TX_IV_0_CHECK
>for ($count = 1; $count < $max_niu_ivns-1; $count++) {
|| INTR0x60_NIU_TX_IV_${count}_CHECK
|| INTR0x60_NIU_TX_IV_${count}_CHECK), 1,
>for ($ivn = 0; $ivn < $hw_num_ivs; $ivn++) {
.byte INTR0x60_IVN_TO_IG(${ivn})
undefine(`INTR0x60_IVN_TO_IG')dnl
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