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* OpenSPARC T2 Processor File: peu_set_serdes_pll_ratio.s
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#define PEU_SERDES_PLL_MPY__100MHZ 7
#define PEU_SERDES_PLL_MPY__125MHZ 5
#define PEU_SERDES_PLL_MPY__250MHZ 1
peu_set_target_pcie_ref_clk_100MHz:
mov PEU_SERDES_PLL_MPY__100MHZ, %g4
peu_set_target_pcie_ref_clk_125MHz:
mov PEU_SERDES_PLL_MPY__125MHZ, %g4
peu_set_target_pcie_ref_clk_250MHz:
mov PEU_SERDES_PLL_MPY__250MHZ, %g4
#endif /* PCIE_REF_CLK_250 */
#endif /* PCIE_REF_CLK_125 */
#endif /* PCIE_REF_CLK_100 */
#if defined(PCIE_REF_CLK_100) || defined(PCIE_REF_CLK_125) || defined(PCIE_REF_CLK_250)
peu_check_serdes_pll_ratio:
best_set_reg(FIRE_PLC_TLU_CTB_TLR_CSR_A_SERDES_PLL_ADDR, %g2, %g3)
brz %g5, peu_serdes_pll_ratio_already_set
peu_set_serdes_pll_ratio:
stx %g4, [%g3] ! set mpy field for 100Mhz refclk
! do a warm reset to activate the new value, per PRM 16.6.6
setx RESET_GEN, %g2, %g5 ! warm reset reg
add %g0, 0x1, %g7 ! warm reset reg data
peu_kick_wmr_for_serdes_pll_ratio_change:
stx %g7, [%g5] ! Warm Reset
ldx [%g5], %g7 ! Force a delay to wait for WMR
peu_serdes_pll_ratio_already_set:
#endif /*defined(PCIE_REF_CLK_100) || defined(PCIE_REF_CLK_125) || defined(PCIE_REF_CLK_250)*/