* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: isa2_all_fail_fc_3.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
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* ========== Copyright Header End ============================================
.ident "FOCUSCASE: focus.pm,v 1.1 2003/04/23 17:53:39 somePerson Exp somePerson $ /import/n2-aus-dump1/somePerson/dump/24x7/spc_basic_isa2.pl FOCUS_SEED=739887052"
.ident "BY somePerson ON Wed Aug 6 14:28:00 CDT 2003"
.ident "Using Instruction Hash for Focus :$Id: isa2_all_fail_fc_3.s,v 1.3 2007/07/05 21:58:50 drp Exp $"
/************************************************************************
************************************************************************/
setx DIAG_DATA_AREA, %g1, %g3
!# Initialize registers ..
INIT_TH_FP_REG(%l7, %f0, 0x55555555aaaaaaaa)
INIT_TH_FP_REG(%l7, %f2, 0xaaaaaaaa55555555)
INIT_TH_FP_REG(%l7, %f4, 0xfedcba9876543210)
INIT_TH_FP_REG(%l7, %f6, 0x0123456789abcdef)
INIT_TH_FP_REG(%l7, %f8, 0x55aa55aaff00ff00)
INIT_TH_FP_REG(%l7, %f10, 0x1111111111111111)
INIT_TH_FP_REG(%l7, %f12, 0x8888888888888888)
INIT_TH_FP_REG(%l7, %f14, 0xfedcba9876543210)
!# Execute some ALU ops ..
tsubcctv %l1, 0x179D, %o6
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
faligndata %f10, %f14, %f8
setx 0x34400001400, %l0, %l1
fandnot2s %f14, %f1, %f11
tsubcctv %l1, 0x1B44, %l0
fandnot2s %f4, %f15, %f12
setx 0x34400001400, %l0, %l1
fmul8ulx16 %f10, %f0, %f4
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
tsubcctv %o5, 0x1D65, %l5
taddcctv %l1, 0x11FE, %l3
taddcctv %g5, 0x0EA1, %l0
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!# Initialize registers ..
INIT_TH_FP_REG(%l7, %f0, 0x55555555aaaaaaaa)
INIT_TH_FP_REG(%l7, %f2, 0xaaaaaaaa55555555)
INIT_TH_FP_REG(%l7, %f4, 0xfedcba9876543210)
INIT_TH_FP_REG(%l7, %f6, 0x0123456789abcdef)
INIT_TH_FP_REG(%l7, %f8, 0x55aa55aaff00ff00)
INIT_TH_FP_REG(%l7, %f10, 0x1111111111111111)
INIT_TH_FP_REG(%l7, %f12, 0x8888888888888888)
INIT_TH_FP_REG(%l7, %f14, 0xfedcba9876543210)
!# Execute some ALU ops ..
setx 0x34400001400, %l0, %l1
fandnot1 %f12, %f10, %f14
tsubcctv %o4, 0x161D, %g3
fmovrsgez %i5, %f12, %f12
fmovsneg %xcc, %f13, %f15
setx 0x34400001400, %l0, %l1
fmuld8ulx16 %f9, %f6, %f4
fmul8ulx16 %f6, %f12, %f14
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fmul8x16au %f4, %f6, %f14
setx 0x34400001400, %l0, %l1
fmul8x16au %f6, %f15, %f8
fmul8x16al %f2, %f12, %f12
fmul8sux16 %f0, %f0, %f12
setx 0x34400001400, %l0, %l1
fmovdpos %icc, %f14, %f14
fmuld8sux16 %f2, %f3, %f0
tsubcctv %i2, 0x0F45, %g2
fmul8ulx16 %f4, %f10, %f4
tsubcctv %i0, 0x1493, %i4
fmuld8sux16 %f4, %f15, %f6
fmovspos %icc, %f12, %f10
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fmuld8sux16 %f14, %f13, %f0
fmovsleu %icc, %f13, %f13
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fmovsneg %icc, %f15, %f14
setx 0x34400001400, %l0, %l1
taddcctv %i3, 0x1FC0, %g1
setx 0x34400001400, %l0, %l1
faligndata %f10, %f4, %f14
fmovdleu %icc, %f15, %f10
setx 0x34400001400, %l0, %l1
fmuld8ulx16 %f2, %f13, %f4
fandnot2 %f10, %f12, %f10
fmul8x16au %f2, %f12, %f2
fandnot2s %f11, %f14, %f3
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!# Initialize registers ..
INIT_TH_FP_REG(%l7, %f0, 0x55555555aaaaaaaa)
INIT_TH_FP_REG(%l7, %f2, 0xaaaaaaaa55555555)
INIT_TH_FP_REG(%l7, %f4, 0xfedcba9876543210)
INIT_TH_FP_REG(%l7, %f6, 0x0123456789abcdef)
INIT_TH_FP_REG(%l7, %f8, 0x55aa55aaff00ff00)
INIT_TH_FP_REG(%l7, %f10, 0x1111111111111111)
INIT_TH_FP_REG(%l7, %f12, 0x8888888888888888)
INIT_TH_FP_REG(%l7, %f14, 0xfedcba9876543210)
!# Execute some ALU ops ..
fmuld8sux16 %f5, %f8, %f14
tsubcctv %o2, 0x179E, %i4
fmul8x16au %f4, %f10, %f14
fmul8x16au %f7, %f15, %f0
fmovsneg %xcc, %f15, %f10
fmul8x16al %f11, %f9, %f14
tsubcctv %l6, 0x1B29, %g7
fpsub16s %f11, %f14, %f10
setx 0x34400001400, %l0, %l1
fmul8sux16 %f0, %f2, %f14
setx 0x34400001400, %l0, %l1
fmul8sux16 %f2, %f12, %f4
fmul8ulx16 %f14, %f4, %f2
tsubcctv %l1, 0x003D, %i5
setx 0x34400001400, %l0, %l1
tsubcctv %l6, 0x0A45, %o1
fandnot1s %f15, %f10, %f0
fmuld8sux16 %f7, %f15, %f14
fandnot1s %f12, %f7, %f12
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!# Initialize registers ..
INIT_TH_FP_REG(%l7, %f0, 0x55555555aaaaaaaa)
INIT_TH_FP_REG(%l7, %f2, 0xaaaaaaaa55555555)
INIT_TH_FP_REG(%l7, %f4, 0xfedcba9876543210)
INIT_TH_FP_REG(%l7, %f6, 0x0123456789abcdef)
INIT_TH_FP_REG(%l7, %f8, 0x55aa55aaff00ff00)
INIT_TH_FP_REG(%l7, %f10, 0x1111111111111111)
INIT_TH_FP_REG(%l7, %f12, 0x8888888888888888)
INIT_TH_FP_REG(%l7, %f14, 0xfedcba9876543210)
!# Execute some ALU ops ..
fmul8ulx16 %f10, %f0, %f2
fmuld8sux16 %f15, %f11, %f8
setx 0x34400001400, %l0, %l1
fmuld8ulx16 %f5, %f15, %f8
faligndata %f6, %f4, %f12
fmuld8sux16 %f1, %f15, %f4
faligndata %f0, %f10, %f8
fmuld8ulx16 %f15, %f7, %f6
setx 0x34400001400, %l0, %l1
fmuld8sux16 %f12, %f6, %f10
fmul8x16al %f7, %f14, %f4
fmul8sux16 %f4, %f0, %f12
fmovsleu %icc, %f13, %f11
fmul8x16au %f10, %f9, %f2
setx 0x34400001400, %l0, %l1
fmovdpos %xcc, %f13, %f15
fmovrsgez %i4, %f12, %f12
fmuld8sux16 %f3, %f11, %f8
fmuld8ulx16 %f0, %f12, %f10
fmul8x16al %f11, %f14, %f0
fmul8x16al %f2, %f12, %f4
fmovspos %icc, %f12, %f11
setx 0x34400001400, %l0, %l1
fmovrdgez %g1, %f14, %f14
setx 0x34400001400, %l0, %l1
fmul8sux16 %f6, %f6, %f12
fmuld8sux16 %f12, %f1, %f14
fandnot1s %f9, %f15, %f13
fmovrdlez %g5, %f10, %f12
fmovrdlez %o0, %f14, %f12
fmovsleu %xcc, %f14, %f10
setx 0x34400001400, %l0, %l1
fmul8ulx16 %f10, %f6, %f2
fmul8x16au %f1, %f13, %f14
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fmuld8ulx16 %f2, %f3, %f0
fmuld8ulx16 %f6, %f9, %f6
fmovdleu %icc, %f14, %f12
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!# Initialize registers ..
INIT_TH_FP_REG(%l7, %f0, 0x55555555aaaaaaaa)
INIT_TH_FP_REG(%l7, %f2, 0xaaaaaaaa55555555)
INIT_TH_FP_REG(%l7, %f4, 0xfedcba9876543210)
INIT_TH_FP_REG(%l7, %f6, 0x0123456789abcdef)
INIT_TH_FP_REG(%l7, %f8, 0x55aa55aaff00ff00)
INIT_TH_FP_REG(%l7, %f10, 0x1111111111111111)
INIT_TH_FP_REG(%l7, %f12, 0x8888888888888888)
INIT_TH_FP_REG(%l7, %f14, 0xfedcba9876543210)
!# Execute some ALU ops ..
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fpadd32s %f11, %f10, %f11
fmovrslez %l0, %f15, %f12
fmuld8sux16 %f12, %f1, %f0
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fmuld8ulx16 %f7, %f9, %f2
setx 0x34400001400, %l0, %l1
fmovrdgez %i3, %f12, %f12
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fmovrdgez %o7, %f10, %f14
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
tsubcctv %g4, 0x1BDE, %o7
setx 0x34400001400, %l0, %l1
taddcctv %i5, 0x029D, %o1
fmovrdlez %l1, %f12, %f14
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
tsubcctv %o0, 0x1EFB, %g6
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
tsubcctv %g3, 0x0271, %i2
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fandnot2s %f14, %f8, %f13
bpos,a,pt %xcc, loop_1036
bpos,a,pn %xcc, loop_1042
taddcctv %l0, 0x0204, %i1
fmuld8sux16 %f7, %f14, %f6
bpos,a,pn %xcc, loop_1098
fmuld8ulx16 %f2, %f12, %f4
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fmul8x16au %f2, %f13, %f8
setx 0x34400001400, %l0, %l1
bneg,a,pn %icc, loop_1195
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
bshuffle %f12, %f10, %f10
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fmul8x16al %f7, %f15, %f14
setx 0x34400001400, %l0, %l1
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!# Initialize registers ..
INIT_TH_FP_REG(%l7, %f0, 0x55555555aaaaaaaa)
INIT_TH_FP_REG(%l7, %f2, 0xaaaaaaaa55555555)
INIT_TH_FP_REG(%l7, %f4, 0xfedcba9876543210)
INIT_TH_FP_REG(%l7, %f6, 0x0123456789abcdef)
INIT_TH_FP_REG(%l7, %f8, 0x55aa55aaff00ff00)
INIT_TH_FP_REG(%l7, %f10, 0x1111111111111111)
INIT_TH_FP_REG(%l7, %f12, 0x8888888888888888)
INIT_TH_FP_REG(%l7, %f14, 0xfedcba9876543210)
!# Execute some ALU ops ..
setx 0x34400001400, %l0, %l1
bleu,a,pn %xcc, loop_1275
fmovsneg %xcc, %f14, %f14
setx 0x34400001400, %l0, %l1
fmuld8sux16 %f13, %f12, %f0
setx 0x34400001400, %l0, %l1
taddcctv %l6, 0x0692, %i2
fmul8ulx16 %f0, %f14, %f6
fmuld8ulx16 %f15, %f12, %f12
fandnot1s %f14, %f10, %f7
fmul8ulx16 %f14, %f14, %f12
taddcctv %g7, 0x184C, %i0
tsubcctv %l6, 0x1082, %o7
fpadd16s %f15, %f10, %f12
fmul8ulx16 %f14, %f4, %f6
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fmovspos %icc, %f15, %f11
fmuld8ulx16 %f2, %f0, %f2
tsubcctv %i2, 0x138A, %i3
fmuld8sux16 %f15, %f10, %f14
fmovrdlez %o4, %f10, %f12
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!# Initialize registers ..
INIT_TH_FP_REG(%l7, %f0, 0x55555555aaaaaaaa)
INIT_TH_FP_REG(%l7, %f2, 0xaaaaaaaa55555555)
INIT_TH_FP_REG(%l7, %f4, 0xfedcba9876543210)
INIT_TH_FP_REG(%l7, %f6, 0x0123456789abcdef)
INIT_TH_FP_REG(%l7, %f8, 0x55aa55aaff00ff00)
INIT_TH_FP_REG(%l7, %f10, 0x1111111111111111)
INIT_TH_FP_REG(%l7, %f12, 0x8888888888888888)
INIT_TH_FP_REG(%l7, %f14, 0xfedcba9876543210)
!# Execute some ALU ops ..
bpos,a,pn %xcc, loop_1389
fmul8sux16 %f0, %f14, %f4
tsubcctv %o3, 0x1136, %i3
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fmul8x16al %f13, %f12, %f2
tsubcctv %g7, 0x10AC, %o1
setx 0x34400001400, %l0, %l1
bpos,a,pn %icc, loop_1414
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fmul8x16au %f2, %f9, %f10
taddcctv %i5, 0x073A, %o3
taddcctv %i0, 0x0F1A, %o6
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!# Initialize registers ..
INIT_TH_FP_REG(%l7, %f0, 0x55555555aaaaaaaa)
INIT_TH_FP_REG(%l7, %f2, 0xaaaaaaaa55555555)
INIT_TH_FP_REG(%l7, %f4, 0xfedcba9876543210)
INIT_TH_FP_REG(%l7, %f6, 0x0123456789abcdef)
INIT_TH_FP_REG(%l7, %f8, 0x55aa55aaff00ff00)
INIT_TH_FP_REG(%l7, %f10, 0x1111111111111111)
INIT_TH_FP_REG(%l7, %f12, 0x8888888888888888)
INIT_TH_FP_REG(%l7, %f14, 0xfedcba9876543210)
!# Execute some ALU ops ..
fmuld8ulx16 %f15, %f1, %f6
bpos,a,pn %icc, loop_1460
bleu,a,pt %icc, loop_1462
fmul8sux16 %f4, %f8, %f12
setx 0x34400001400, %l0, %l1
fmul8x16au %f14, %f10, %f6
fmuld8sux16 %f1, %f5, %f2
fmul8x16au %f3, %f12, %f2
fmovspos %xcc, %f10, %f11
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fmul8x16au %f13, %f14, %f6
fmovsleu %icc, %f15, %f13
bleu,a,pt %icc, loop_1564
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
fmuld8sux16 %f1, %f11, %f10
setx 0x34400001400, %l0, %l1
fmovdpos %icc, %f10, %f13
faligndata %f14, %f14, %f4
fmuld8ulx16 %f12, %f4, %f0
bleu,a,pn %xcc, loop_1603
fmovrdgez %l5, %f10, %f12
fmuld8ulx16 %f10, %f1, %f4
fandnot1 %f14, %f10, %f12
setx 0x34400001400, %l0, %l1
fpadd32s %f11, %f11, %f13
setx 0x34400001400, %l0, %l1
fmul8x16au %f1, %f15, %f14
bleu,a,pn %icc, loop_1643
fmul8x16al %f6, %f10, %f6
fmul8sux16 %f0, %f12, %f0
setx 0x34400001400, %l0, %l1
fmuld8ulx16 %f0, %f2, %f10
fmul8x16au %f11, %f0, %f10
fmuld8sux16 %f9, %f6, %f4
fmuld8ulx16 %f7, %f3, %f2
setx 0x34400001400, %l0, %l1
fandnot2 %f10, %f14, %f12
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
bneg,a,pt %icc, loop_1729
bpos,a,pn %xcc, loop_1741
fmul8x16al %f13, %f14, %f14
setx 0x34400001400, %l0, %l1
fmovrsgez %l6, %f10, %f10
fandnot1s %f10, %f12, %f1
fpadd32s %f15, %f15, %f12
setx 0x34400001400, %l0, %l1
fandnot1s %f13, %f11, %f12
setx 0x34400001400, %l0, %l1
fmovrsgez %l6, %f14, %f12
setx 0x34400001400, %l0, %l1
fmul8x16al %f8, %f3, %f12
bleu,a,pn %xcc, loop_1803
fmovspos %xcc, %f13, %f13
bneg,a,pt %icc, loop_1815
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
faligndata %f12, %f10, %f14
fmuld8ulx16 %f4, %f11, %f0
fmuld8ulx16 %f1, %f15, %f2
setx 0x34400001400, %l0, %l1
fmuld8ulx16 %f11, %f0, %f10
setx 0x34400001400, %l0, %l1
fmuld8ulx16 %f9, %f2, %f6
fmul8sux16 %f12, %f12, %f2
setx 0x34400001400, %l0, %l1
fmul8ulx16 %f6, %f12, %f10
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
setx 0x34400001400, %l0, %l1
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
EXIT_GOOD /* test finish */
/************************************************************************
************************************************************************/