* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: PCIeDrainState.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
* available with the language indicating that GPLv2 or any later version
* may be used, or where a choice of which version of the GPL is applied is
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
* CA 95054 USA or visit www.sun.com if you need additional information or
* ========== Copyright Header End ============================================
#define ENABLE_PCIE_LINK_TRAINING
#define MAIN_PAGE_HV_ALSO
#define H_HT0_Data_access_error_0x32
#define SUN_H_HT0_Data_access_error_0x32 \
#include "dmu_peu_regs.h"
#define MEM_WR_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
#define DMA_DATA_ADDR 0x0000000123456000
#define DMARD_ADDR1 0xfffc000123456000
#define DMARD_ADDR2 0xfffc000123457000
#define DMARD_ADDR3 0xfffc000123458000
#define DMARD_ADDR4 0xfffc000123459000
! make sure the detect.quiet bit is set
setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g3
orcc %g5, %g4, %g5 ! OR in bit 8 == 1
/************************************************************
Fire off some PIOs and DMA Reads, then bring down the link.
************************************************************/
DmaRd1: setx MEM_WR_ADDR, %g1, %g2
! $EV trig_pc_d(1, @VA(.MAIN.DmaRd1)) -> EnablePCIeIgCmd("DMARD",DMARD_ADDR1,DMARD_ADDR1,"64'h40",1)
DmaRd2: setx 0x3335373992828384, %g1, %l0
! $EV trig_pc_d(1, @VA(.MAIN.DmaRd2)) -> EnablePCIeIgCmd("DMARD",DMARD_ADDR2,DMARD_ADDR2,"64'h40",1)
! here is where we bring down the link, to force an error
setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g1, %g2
stx %g3, [%g2] ! clear any OE status bits
nop ! $EV trig_pc_d(1, @VA(.MAIN.Bring_down_the_link)) -> EnablePCIeIgCmd("LINKDOWN",0,0,0,1)
! now wait for the "link down" primary or secondary status to be set
setx 0x0000020000000200, %g1, %l1 ! mask for Link Down Primary and Secondary Events
brnz %l0, Wait_for_link_down
/************************************************************
check that drain.state bit is set in the PEU Status Register
************************************************************/
! This user event will force the next PIO to NOT to call expectPCIE().
! $EV trig_pc_d(1,@VA(.MAIN.Check_drain_state)) -> EnablePCIeIgCmd("PIO_NOEXP",0,0,0,1)
setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_STS_ADDR, %g1, %g3
bz test_failed ! branch if drain state is not set
! issue PIO read request(s) - these should complete with Bus Error
setx MEM_WR_ADDR, %g1, %g4
ldx [%g4], %l3 ! ==> this should get a bus error
dec %l4 ! <== only one interrupt expected
! insure that no outstanding DMA read requests are outstanding
! by checking that there are no entries on the Transaction Scoreboard
setx FIRE_DLC_TSB_CSR_A_TSB_STS_ADDR, %g1, %g5
bnz Wait_for_dma_read_clear
! clear the link down bit from the Other Error clear reg
brnz %l1, test_failed ! branch if link down is not cleared
! clear the drain bit from the PEU Status reg
bnz test_failed ! branch if drain state is not cleared
! clear any error bits from from the DLPL Status reg
setx FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ADDR, %g1, %g6
brnz %l7, test_failed ! branch if it is not cleared
/************************************************************
Now redo link training...
************************************************************/
nop ! $EV trig_pc_d(1, @VA(.MAIN.redo_link_training)) -> EnablePCIeIgCmd("LINKUP",0,0,0,1)
! clear bit 8, to not remain in Detect.Quiet state
setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g3
! wait for the "Link Up" status bit to get set in the PEU
! (this code copied from peu_init.h)
setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g1, %g3
stx %l4, [%g3] ! clear any status bits that are set
setx FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_ADDR, %g1, %g4
mov FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_EN_ERR__LUP_P, %l1
ldx [%g3], %l4 ! bit 8 is Link Up primary event
ldx [%g4], %l5 ! bits 48:44 are the LTSSM state
brnz %l0, LinkTrainingLoop2
/********************************************************************
Do a couple of PIOs and DMAs to verify that the PCIe link is working.
********************************************************************/
! clear any error bits from from the DLPL Status reg
setx FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ADDR, %g1, %g6
brnz %l7, test_failed ! branch if it is not cleared
setx MEM_WR_ADDR, %g1, %g5
! $EV trig_pc_d(1, @VA(.MAIN.DmaRd3)) -> EnablePCIeIgCmd("DMARD",DMARD_ADDR3,DMARD_ADDR3,"64'h40",1)
stx %g3, [%g5+24] ! 3 PIO Writes
! $EV trig_pc_d(1, @VA(.MAIN.DmaRd4)) -> EnablePCIeIgCmd("DMARD",DMARD_ADDR4,DMARD_ADDR4,"64'h40",1)
ldx [%g5+24], %l0 ! 3 PIO Reads
ldx [%g3], %l5 ! bit 8 is Link Up primary event
ldx [%g4], %l6 ! bits 48:44 are the LTSSM state
ldx [%g6], %l7 ! dlpl status
brnz %l4, test_failed ! no interrupts were expected
SECTION .DATA DATA_VA=DMA_DATA_ADDR
.xword 0x0101010101010101
.xword 0x0101010101010101
.xword 0x0101010101010101
.xword 0x0101010101010101
.xword 0x0101010101010101
.xword 0x0101010101010101
.xword 0x0101010101010101
.xword 0x0101010101010101
.xword 0x0202020202020202
.xword 0x0202020202020202
.xword 0x0202020202020202
.xword 0x0202020202020202
.xword 0x0202020202020202
.xword 0x0202020202020202
.xword 0x0202020202020202
.xword 0x0202020202020202
.xword 0x0303030303030303
.xword 0x0303030303030303
.xword 0x0303030303030303
.xword 0x0303030303030303
.xword 0x0303030303030303
.xword 0x0303030303030303
.xword 0x0303030303030303
.xword 0x0303030303030303
.xword 0x0404040404040404
.xword 0x0404040404040404
.xword 0x0404040404040404
.xword 0x0404040404040404
.xword 0x0404040404040404
.xword 0x0404040404040404
.xword 0x0404040404040404
.xword 0x0404040404040404
/************************************************************************/