* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: PCIeMem64AdrCov.s
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* ========== Copyright Header End ============================================
#define ENABLE_PCIE_LINK_TRAINING
#define MAIN_PAGE_HV_ALSO
#define MEM64_BASE mpeval(N2_PCIE_BASE_ADDR + (MEM64_OFFSET_BASE_REG_DATA & 0x7fffffffffffffff))
#define MEM64_RD_ADDR0 MEM64_BASE
!! For MEM64, the pcie spec says you need a bit set in 63-32
#define MEM64_OFFSET_WALK1 0x0100000001000000
#define BNE_TEST_FAIL bne test_failed
#define BNE_TEST_FAIL nop
/************************************************************************
************************************************************************/
! Load the PCIE MEM64 OFFSET Register address
setx FIRE_DLC_IMU_ICS_CSR_A_MEM_64_PCIE_OFFSET_REG_ADDR, %g1, %g2
! Get the initial walking 1 and 0 values
setx MEM64_OFFSET_WALK1, %g1, %g3
setx MEM64_RD_ADDR0, %g1, %g6 ! PIO MEM64 address
setx 0x0102030405060708, %g1, %g7 ! data value
setx 0x1020304050607080, %g1, %l0 ! data value
setx 0x0101010101010101, %g1, %o0 ! data increment value
stx %g3, [%g2] ! set the walking 1 mem 64 offset value
ldx [%g2], %g4 ! make sure write has completed
stx %g7,[%g6 + 0] ! pio mem 64 write
stx %l0,[%g6 + 8] ! pio mem 64 write
ldx [%g6], %l1 ! pio mem 64 read
ldx [%g6 + 8], %l2 ! pio mem 64 read
sllx %g3, 1, %g3 ! shift walking 1 value left by 1
add %g7, %o0, %g7 ! increment data patterns
dec %g5 ! decrement counter
brnz %g5, SetMem64Offset ! loop if not zero