* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: PCIeMsi.s
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* ========== Copyright Header End ============================================
#define ENABLE_PCIE_LINK_TRAINING
#define MAIN_PAGE_HV_ALSO
/************************************************************************
************************************************************************/
setx 0x00000000cccccccc, %g1, %g2 !!!! Set up MSI32 address -must be 4 byte aligned
setx FIRE_DLC_IMU_ICS_CSR_A_MSI_32_ADDR_REG_ADDR, %g1, %g3
setx 0xffffffffffffffff, %g1, %g2 !!!! Enable IMU error Logging
setx FIRE_DLC_IMU_ICS_CSR_A_IMU_ERROR_LOG_EN_REG_ADDR, %g1, %g3
!setx 0xffffffffffffffff, %g1, %g2 !!!! Enable IMU error Interrupts
setx FIRE_DLC_IMU_ICS_CSR_A_IMU_INT_EN_REG_ADDR, %g1, %g3
!!!! Make sure that any status bits are cleared
setx FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_ADDR, %g1, %g3
ldx [%g3], %g4 !!! a read should force all writes to complete
! $EV trig_pc_d(1, @VA(.MAIN.MSI32_Evnt)) -> EnablePCIeIgCmd ("MSI32", 00000000000000ff, 0, 4, 1 )
! now poll for the MSI event
setx FIRE_DLC_IMU_ICS_CSR_A_IMU_ENABLED_ERROR_STATUS_REG_ADDR, %g1, %g2
setx FIRE_DLC_IMU_ICS_CSR_A_IMU_RDS_ERROR_LOG_REG_ADDR, %g1, %g3
ldx [%g3], %g2 !!!! Read the IMU RDS Error Log Register
setx 0xaabbccddeeff3344, %g1, %g2 !!!! Set up MSI64 address -must be 4 byte aligned
setx FIRE_DLC_IMU_ICS_CSR_A_MSI_64_ADDR_REG_ADDR, %g1, %g3
setx 0xffffffffffffffff, %g1, %g2 !!!! Make sure that any status bits are cleared
setx FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_ADDR, %g1, %g3
ldx [%g3], %g4 !!! a read should force all writes to complete
! $EV trig_pc_d(1, @VA(.MAIN.MSI64_Evnt2)) -> EnablePCIeIgCmd ("MSI64", 00000000000000ee, 0, 4, 1 )
! now poll for the MSI event
setx FIRE_DLC_IMU_ICS_CSR_A_IMU_ENABLED_ERROR_STATUS_REG_ADDR, %g1, %g2
setx FIRE_DLC_IMU_ICS_CSR_A_IMU_RDS_ERROR_LOG_REG_ADDR, %g1, %g3
ldx [%g3], %g2 !!!! Read the IMU RDS Error Log Register