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* OpenSPARC T2 Processor File: err_ittp_diag.s
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#define MY_HP_TEXT_PA 0x1050000000
#define MY_HP_DATA_PA 0x1050001000
#define ASI_PRIMARY_CONTEXT_0 0x21
#define ASI_ITLB_DATA_IN_REG 0x54
#define ASI_DMMU_TAG_ACCESS 0x58
#define ASI_DTLB_DATA_IN_REG 0x5c
#define ASI_DMMU_SFAR 0x58
#define MY_USER_TEXT_VA000 0x7a000000
#define MY_USER_TEXT_RA000 0x7b000000
#define MY_USER_TEXT_PA000 0x107b000000
#define MY_USER_TEXT_VA001 0x7a010000
#define MY_USER_TEXT_RA001 0x7b010000
#define MY_USER_TEXT_PA001 0x107b010000
#define MY_USER_DATA_VA000 0x6a000000
#define MY_USER_DATA_RA000 0x6b000000
#define MY_USER_DATA_PA000 0x106b000000
#define MY_USER_DATA_VA001 0x6a010000
#define MY_USER_DATA_RA001 0x6b010000
#define MY_USER_DATA_PA001 0x106b010000
#define MAIN_PAGE_HV_ALSO
!! enable error detcetion. Disable error injection.
#define H_HT0_Mem_Address_Not_Aligned_0x34
#define My_HT0_Mem_Address_Not_Aligned_0x34 \
add %g0, CERER_VA, %g3; \
stxa %o2, [%g3]ASI_CERER; \
stxa %g0, [%g0]ASI_ERR_INJ; \
#define H_HT0_Data_Access_MMU_Error_0x72
#define SUN_H_HT0_Data_Access_MMU_Error_0x72 \
ba DATA_ACCESS_ERROR_HANDLER; \
nop;nop;nop;nop;nop;nop;nop
#define H_HT0_Instruction_Access_MMU_Error_0x71
#define SUN_H_HT0_Instruction_Access_MMU_Error_0x71 \
ba INST_ACCESS_MMU_ERROR_HANDLER; \
nop;nop;nop;nop;nop;nop;nop
/************************************************************************
************************************************************************/
!! Enable err_injection and err_detection. The pg to which we are jumping
!! is a tLB miss, it will be loaded in TLB with err injected and then
!! on the TLB lookup error will be seen. When we first lookup the pg, it is
!! a TLB miss. The err_hanlder clears error detection but err_injection is
!!on so pg is reloaded with parity err.
!! Enable error injection
setx ERR_INJ_REG_DATA, %l0, %l1
stxa %l1, [%g0]ASI_ERR_INJ
setx CERER_DATA, %l0, %o2
setx user_code_begin_000, %g1, %l4
/************************************************************************
************************************************************************/
!#***********************************************************************
SECTION .My_User_Section_4v000 TEXT_VA=MY_USER_TEXT_VA000, DATA_VA=MY_USER_DATA_VA000
Name = .My_User_Section_4v000,
part_0_ctx_nonzero_tsb_config_2,
PA = ra2pa(MY_USER_TEXT_RA000, 0),
!! Take mis aligned trap. The trap handler enables err_detection and
!! clears err_injection. On return from trap handler, mmu_err trap is
!! taken for label TH0_done. The pg is reloaded with no err.
.global user_code_begin_000
setx user_data_begin_000, %g1, %l3
ld [%l3+1], %g1 !cause mem_addr_not_aligned trap
setx user_code_begin_001, %g1, %l4
Name = .My_User_Section_4v000,
part_0_ctx_nonzero_tsb_config_1,
PA = ra2pa(MY_USER_DATA_RA000, 0),
.global user_data_begin_000
SECTION .My_User_Section_4v001 TEXT_VA=MY_USER_TEXT_VA001, DATA_VA=MY_USER_DATA_VA001
Name = .My_User_Section_4v001,
part_0_ctx_nonzero_tsb_config_2,
PA = ra2pa(MY_USER_TEXT_RA001, 0),
NAME = .My_User_Section_4v001,
!! Chk if there is an err in the delay slot and delay slot is annulled
!! then err is not reported.
!! pg _001 has no error. Lable TGT0 represents the first inst. of
!! next_page and TGT1 represents the 2nd inst.
!! There are two iterations, in the first iteration inst in delay slot is
!! executed and causes pg to be loaded with err in tlb. Alignment trap
!! is taken that causes err_detection to be enabled. On return from
!!trap handler the delay slot inst has an err but it is not reported as
!! the delay slot os annulled.
.global user_code_begin_001
mov %g0, %i1 ! to control branch execution
!! Enable error injection
stxa %l1, [%g0]ASI_ERR_INJ
setx user_data_begin_000, %g1, %l3
GO_BACK: brz,a %i1, TGT1 !! load entry in ITLB
TGT0: add %g0, %g7, %g5 !! dummy inst
ld [%l3+1], %g1 !cause mem_addr_not_aligned trap
Name = .My_User_Section_4v001,
part_0_ctx_nonzero_tsb_config_1,
PA = ra2pa(MY_USER_DATA_RA001, 0),
NAME = .My_User_Section_4v001,
.global user_data_begin_001
.global DATA_ACCESS_ERROR_HANDLER
.global INST_ACCESS_ERROR_HANDLER
DATA_ACCESS_ERROR_HANDLER:
ldxa [%g5]ASI_DSFSR, %o1 !
add %g0, SFAR_VA, %g6 !!g6 has sfar va
stxa %g0, [%o1] ASI_DMMU_DEMAP
INST_ACCESS_MMU_ERROR_HANDLER:
ldxa [%g5]ASI_ISFSR, %o1 !
add %g0, SFAR_VA, %g6 !!g6 has sfar va
cmp %o1, %l4 !! cmp pc matches the expected pc
stxa %g0, [%o1] ASI_IMMU_DEMAP