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* OpenSPARC T2 Processor File: tlu_allintvec1.s
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#define MAIN_PAGE_HV_ALSO
#define MAIN_PAGE_NUCLEUS_ALSO
#define H_HT0_Interrupt_0x60
#define My_HT0_Interrupt_0x60 \
ldxa [%g0] ASI_SWVR_INTR_RECEIVE, %g1 ;\
ldxa [%g0] ASI_SWVR_INTR_R, %g2 ;\
ldxa [%g0] ASI_SWVR_INTR_RECEIVE, %g3 ;\
andn %o1, 7, %o1 ! %o1 has Core ID
! Disable all threads (in my core) ..
stxa %g2, [%g1]ASI_CMP_CORE
stxa %g3, [%g0]ASI_SWVR_UDB_INTR_W
! Wake up all threads (in my core) ..
stxa %g2, [%g1]ASI_CMP_CORE