// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: vuaderr.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
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// ========== Copyright Header End ============================================
module vuaderr(L2_INT_RST);
reg [38:0] vld_dirty, usaloc, buffer;
reg vd_inject_err,ua_inject_err,vd_inject_ue,ua_inject_ue,trph;
wire [39:0] arbdp_addr_c1;
wire [6:0] vd_ecc_c1,ua_ecc_c1;
wire [15:0] valid_c1,dirty_c1,used_c1,alloc_c1;
wire inst_vld_c2_prev,vuad_vlddir_no_bypass_c1,vuad_usaloc_no_bypass_c1,arb_inst_diag_c1;
wire take_eer,take_retry;
assign arbdp_addr_c1 = tb_top.cpu.l2t0.arbadr.arbdp_addr_c1_1;
assign inst_vld_c2_prev = tb_top.cpu.l2t0.arb.inst_vld_c2_prev;
assign vuad_vlddir_no_bypass_c1=tb_top.cpu.l2t0.vlddir.mux_valid_dirty_c1_sel0;
assign arb_inst_diag_c1 = tb_top.cpu.l2t0.arb.arb_inst_diag_c1;
assign vd_ecc_c1 = tb_top.cpu.l2t0.vlddir.vuad_array_rd_data_c1[38:32];
assign valid_c1 = tb_top.cpu.l2t0.vlddir.valid_c1;
assign dirty_c1 = tb_top.cpu.l2t0.vlddir.dirty_c1;
assign vuad_usaloc_no_bypass_c1 = tb_top.cpu.l2t0.usaloc.vuad_usaloc_mux_used_and_alloc_comb_sel5;
assign ua_ecc_c1 = tb_top.cpu.l2t0.usaloc.vuad_array_rd_data_c1[77:71];
assign used_c1 = tb_top.cpu.l2t0.usaloc.used_c1;
assign alloc_c1 = tb_top.cpu.l2t0.usaloc.alloc_c1;
assign take_retry = tb_top.cpu.spc0.tlu.trl0.take_ret;
assign take_eer = tb_top.cpu.spc0.tlu.trl0.take_eer; // For Hw Corr
if($test$plusargs("PREFICE_VD_INJECT"))
$display("MSA1: forcing_err\n");
@(posedge tb_top.cpu.l2t0.arbdec.pf_ice_qual);
$display("MSA2: forcing_err\n");
@(posedge tb_top.cpu.l2t0.arbdec.pf_ice_qual);
$display("MSA3: forcing_err\n");
@(posedge tb_top.cpu.l2t0.arbdec.pf_ice_qual);
@(posedge tb_top.cpu.l2t0.arbdec.pf_ice_qual);
@(posedge tb_top.cpu.l2t0.arbdec.pf_ice_qual);
$display("BAS: force the valid bits\n");
@(posedge tb_top.cpu.l2clk);
$display("BAS: force the valid bits\n");
force tb_top.cpu.l2t0.vlddir.valid_c2[15:0] = 16'h0000;
force tb_top.cpu.l2t0.vlddir.vlddir_vuad_valid_c2[15:0] = 16'h0000;
@(posedge tb_top.cpu.l2clk);
release tb_top.cpu.l2t0.vlddir.valid_c2[15:0];
@(negedge tb_top.cpu.l2clk);
release tb_top.cpu.l2t0.vlddir.vlddir_vuad_valid_c2[15:0];
$display("BAS: release the valid bits\n");
//=================================
// Initialize the variables used in here
//=================================
//=========================================
// Check if forcing variables are changed by verargs
//=========================================
if($test$plusargs("L2VD_CE_ERR_INJECT"))
`PR_ALWAYS("l2err_injector", `ALWAYS, "L2 VD Err injector enabled");
else if($test$plusargs("L2UA_CE_ERR_INJECT"))
`PR_ALWAYS("l2err_injector", `ALWAYS, "L2 UA Err injector enabled");
if($test$plusargs("L2VD_UE_INJECT"))
`PR_ALWAYS("l2err_injector", `ALWAYS, "L2 VD Err injector enabled");
else if($test$plusargs("L2UA_UE_INJECT"))
`PR_ALWAYS("l2err_injector", `ALWAYS, "L2 UA Err injector enabled");
always @(posedge tb_top.cpu.l2clk)
if(`TOP.gOutOfBoot[63:0] === `TOP.verif_args.finish_mask[63:0] )
//Sequential part of stmc...
//To not inject in traphandler
always @(posedge tb_top.cpu.l2clk)
if(ua_inject_ue || vd_inject_ue || vd_inject_err || ua_inject_err)
if(!L2_INT_RST) cs <= s0;
always @(s0 or s1 or take_eer or take_retry or cs or ua_inject_ue or vd_inject_ue or vd_inject_err or ua_inject_err)
if(ua_inject_ue || vd_inject_ue || vd_inject_err || ua_inject_err)
if ( take_eer == 0) ns <= s0;
else if (take_eer == 1) begin ns <= s1; trph<= 1;end
if (take_retry == 0)begin ns <= s1; trph <= 1; end
else if (take_retry == 1) begin ns <= s0;trph<=0;end
//$display("In Combo Logic take_retry=%d,take_eer=%d,trph=%d,ns=%d",take_retry,take_eer,trph,ns);
always @(posedge tb_top.cpu.l2clk)
if((`TOP.gOutOfBoot[63:0] === `TOP.verif_args.finish_mask[63:0]) && ( vd_inject_err == 1 || vd_inject_ue == 1) && !trph)
//$display("Before if inst_vld_c2_prev=%d,vuad_vlddir_no_bypass_c1=%d,arb_inst_diag_c1=%d, bit_pos = %b",inst_vld_c2_prev,vuad_vlddir_no_bypass_c1,arb_inst_diag_c1,bit_pos);
if(inst_vld_c2_prev && vuad_vlddir_no_bypass_c1 && !arb_inst_diag_c1 && bit_pos[3] != 1)
//$display("After if inst_vld_c2_prev=%d,vuad_vlddir_no_bypass_c1=%d,arb_inst_diag_c1=%d",inst_vld_c2_prev,vuad_vlddir_no_bypass_c1,arb_inst_diag_c1);
address <= arbdp_addr_c1; // C1 signal
if($test$plusargs("L2PM_fourbank"))
else if($test$plusargs("L2PM_twobank"))
else index <= address[17:9];
vld_dirty= {vd_ecc_c1,valid_c1,dirty_c1};
cnt <= ({$random(`PARGS.seed)} % 39);
//$display("address=%h,index=%h,vld_dirty=%d,i=%d",address,index,vld_dirty,i);
vld_dirty[cnt] <= vld_dirty[cnt] ^ 1'b1;
if(vd_inject_ue) vld_dirty[cnt+1] <= vld_dirty[cnt+1] ^ 1'b1;
@(posedge tb_top.cpu.l2clk);
SetVldDirtyVuadArrayC2(i, vld_dirty);
if(vd_inject_err) `PR_ALWAYS("l2err_injector", `ALWAYS,"VUAD CE injected (VD) in bank%d, Index%d, bit%dflipped (address = %x)\n\n", i, index, cnt, address);
else `PR_ALWAYS("l2err_injector", `ALWAYS,"VUAD UE injected (VD) in bank%d, Index%d, bit%dflipped (address = %x)\n\n", i, index, cnt, address);
@(posedge tb_top.cpu.l2clk);
ReleaseVldDirtyVuadArrayC2(i);
end // if(inst_vld_c2_prev && vuad_vlddir_no_bypass_c1 && !arb_inst_diag_c1)
@(posedge tb_top.cpu.l2clk);
end //else of if(!L2_INT_RST)
end //always @(posedge tb_top.cpu.l2clk)
/*** end of VD error injection**/
/*** Start of UA error injection**/
always @(posedge tb_top.cpu.l2clk)
if((`TOP.gOutOfBoot[63:0] === `TOP.verif_args.finish_mask[63:0] ) && ( ua_inject_err == 1 || ua_inject_ue == 1) && !trph)
//if(.$array_rd_en){ // This is a PX2 signal
//repeat(2)@(posedge tb_top.cpu.l2clk);
if(inst_vld_c2_prev && vuad_usaloc_no_bypass_c1 && !arb_inst_diag_c1 && bit_pos[3] != 1)
address = arbdp_addr_c1; // C1 signal
if($test$plusargs("L2PM_fourbank"))
else if($test$plusargs("L2PM_twobank"))
else index <= address[17:9];
usaloc = {ua_ecc_c1, used_c1, alloc_c1};
cnt =({$random(`PARGS.seed)} % 39);
usaloc[cnt] = usaloc[cnt] ^ 1'b1;
if(ua_inject_ue) usaloc[cnt+1] = usaloc[cnt+1] ^ 1'b1;
@(posedge tb_top.cpu.l2clk);
SetUsAlocVuadArrayC2(i, usaloc);
if(ua_inject_err) `PR_ALWAYS("l2err_injector", `ALWAYS,"VUAD CE injected (UA) in Bank 0, Index%d, bit%d flipped (address = %x)\n\n", index, cnt, address);
else `PR_ALWAYS("l2err_injector", `ALWAYS,"VUAD UE injected (UA) in Bank 0, Index%d, bit%d flipped (address = %x)\n\n", index, cnt, address);
@(posedge tb_top.cpu.l2clk);
ReleaseUsalocVuadArrayC2(i);
buffer[cnt] = buffer[cnt] ^ 1'b1;
end //if(inst_vld_c2_prev && vuad_usaloc_no_bypass_c1 && !arb_inst_diag_c1)
@(posedge tb_top.cpu.l2clk);
end ////else of if(!L2_INT_RST)
end //always @(posedge tb_top.cpu.l2clk)
//Tasks Used By Error Injector
task SetVldDirtyVuadArrayC2;
force tb_top.cpu.l2t0.vlddir.vd_ecc_c2[6:0] = value[38:32];
force tb_top.cpu.l2t0.vlddir.valid_c2[15:0] = value[31:16];
force tb_top.cpu.l2t0.vlddir.dirty_c2[15:0] = value[15:0];
force tb_top.cpu.l2t1.vlddir.vd_ecc_c2[6:0] = value[38:32];
force tb_top.cpu.l2t1.vlddir.valid_c2[15:0] = value[31:16];
force tb_top.cpu.l2t1.vlddir.dirty_c2[15:0] = value[15:0];
force tb_top.cpu.l2t2.vlddir.vd_ecc_c2[6:0] = value[38:32];
force tb_top.cpu.l2t2.vlddir.valid_c2[15:0] = value[31:16];
force tb_top.cpu.l2t2.vlddir.dirty_c2[15:0] = value[15:0];
force tb_top.cpu.l2t3.vlddir.vd_ecc_c2[6:0] = value[38:32];
force tb_top.cpu.l2t3.vlddir.valid_c2[15:0] = value[31:16];
force tb_top.cpu.l2t3.vlddir.dirty_c2[15:0] = value[15:0];
force tb_top.cpu.l2t4.vlddir.vd_ecc_c2[6:0] = value[38:32];
force tb_top.cpu.l2t4.vlddir.valid_c2[15:0] = value[31:16];
force tb_top.cpu.l2t4.vlddir.dirty_c2[15:0] = value[15:0];
force tb_top.cpu.l2t5.vlddir.vd_ecc_c2[6:0] = value[38:32];
force tb_top.cpu.l2t5.vlddir.valid_c2[15:0] = value[31:16];
force tb_top.cpu.l2t5.vlddir.dirty_c2[15:0] = value[15:0];
force tb_top.cpu.l2t6.vlddir.vd_ecc_c2[6:0] = value[38:32];
force tb_top.cpu.l2t6.vlddir.valid_c2[15:0] = value[31:16];
force tb_top.cpu.l2t6.vlddir.dirty_c2[15:0] = value[15:0];
force tb_top.cpu.l2t7.vlddir.vd_ecc_c2[6:0] = value[38:32];
force tb_top.cpu.l2t7.vlddir.valid_c2[15:0] = value[31:16];
force tb_top.cpu.l2t7.vlddir.dirty_c2[15:0] = value[15:0];
// force tb_top.force_vd = 1'b1;
task ReleaseVldDirtyVuadArrayC2;
release tb_top.cpu.l2t0.vlddir.vd_ecc_c2[6:0];
release tb_top.cpu.l2t0.vlddir.valid_c2[15:0];
release tb_top.cpu.l2t0.vlddir.dirty_c2[15:0];
release tb_top.cpu.l2t1.vlddir.vd_ecc_c2[6:0];
release tb_top.cpu.l2t1.vlddir.valid_c2[15:0];
release tb_top.cpu.l2t1.vlddir.dirty_c2[15:0];
release tb_top.cpu.l2t2.vlddir.vd_ecc_c2[6:0];
release tb_top.cpu.l2t2.vlddir.valid_c2[15:0];
release tb_top.cpu.l2t2.vlddir.dirty_c2[15:0];
release tb_top.cpu.l2t3.vlddir.vd_ecc_c2[6:0];
release tb_top.cpu.l2t3.vlddir.valid_c2[15:0];
release tb_top.cpu.l2t3.vlddir.dirty_c2[15:0];
release tb_top.cpu.l2t4.vlddir.vd_ecc_c2[6:0];
release tb_top.cpu.l2t4.vlddir.valid_c2[15:0];
release tb_top.cpu.l2t4.vlddir.dirty_c2[15:0];
release tb_top.cpu.l2t5.vlddir.vd_ecc_c2[6:0];
release tb_top.cpu.l2t5.vlddir.valid_c2[15:0];
release tb_top.cpu.l2t5.vlddir.dirty_c2[15:0];
release tb_top.cpu.l2t6.vlddir.vd_ecc_c2[6:0];
release tb_top.cpu.l2t6.vlddir.valid_c2[15:0];
release tb_top.cpu.l2t6.vlddir.dirty_c2[15:0];
release tb_top.cpu.l2t7.vlddir.vd_ecc_c2[6:0];
release tb_top.cpu.l2t7.vlddir.valid_c2[15:0];
release tb_top.cpu.l2t7.vlddir.dirty_c2[15:0];
// force tb_top.force_vd = 1'b0;
task SetUsAlocVuadArrayC2;
force tb_top.cpu.l2t0.usaloc.ua_ecc_c2[6:0] = value[38:32];
force tb_top.cpu.l2t0.usaloc.used_c2[15:0] = value[31:16];
force tb_top.cpu.l2t0.usaloc.alloc_c2[15:0] = value[15:0];
force tb_top.cpu.l2t1.usaloc.ua_ecc_c2[6:0] = value[38:32];
force tb_top.cpu.l2t1.usaloc.used_c2[15:0] = value[31:16];
force tb_top.cpu.l2t1.usaloc.alloc_c2[15:0] = value[15:0];
force tb_top.cpu.l2t2.usaloc.ua_ecc_c2[6:0] = value[38:32];
force tb_top.cpu.l2t2.usaloc.used_c2[15:0] = value[31:16];
force tb_top.cpu.l2t2.usaloc.alloc_c2[15:0] = value[15:0];
force tb_top.cpu.l2t3.usaloc.ua_ecc_c2[6:0] = value[38:32];
force tb_top.cpu.l2t3.usaloc.used_c2[15:0] = value[31:16];
force tb_top.cpu.l2t3.usaloc.alloc_c2[15:0] = value[15:0];
force tb_top.cpu.l2t4.usaloc.ua_ecc_c2[6:0] = value[38:32];
force tb_top.cpu.l2t4.usaloc.used_c2[15:0] = value[31:16];
force tb_top.cpu.l2t4.usaloc.alloc_c2[15:0] = value[15:0];
force tb_top.cpu.l2t5.usaloc.ua_ecc_c2[6:0] = value[38:32];
force tb_top.cpu.l2t5.usaloc.used_c2[15:0] = value[31:16];
force tb_top.cpu.l2t5.usaloc.alloc_c2[15:0] = value[15:0];
force tb_top.cpu.l2t6.usaloc.ua_ecc_c2[6:0] = value[38:32];
force tb_top.cpu.l2t6.usaloc.used_c2[15:0] = value[31:16];
force tb_top.cpu.l2t6.usaloc.alloc_c2[15:0] = value[15:0];
force tb_top.cpu.l2t7.usaloc.ua_ecc_c2[6:0] = value[38:32];
force tb_top.cpu.l2t7.usaloc.used_c2[15:0] = value[31:16];
force tb_top.cpu.l2t7.usaloc.alloc_c2[15:0] = value[15:0];
// force tb_top.force_ua = 1'b1;
task ReleaseUsalocVuadArrayC2;
release tb_top.cpu.l2t0.usaloc.ua_ecc_c2[6:0];
release tb_top.cpu.l2t0.usaloc.used_c2[15:0];
release tb_top.cpu.l2t0.usaloc.alloc_c2[15:0];
release tb_top.cpu.l2t1.usaloc.ua_ecc_c2[6:0];
release tb_top.cpu.l2t1.usaloc.used_c2[15:0];
release tb_top.cpu.l2t1.usaloc.alloc_c2[15:0];
release tb_top.cpu.l2t2.usaloc.ua_ecc_c2[6:0];
release tb_top.cpu.l2t2.usaloc.used_c2[15:0];
release tb_top.cpu.l2t2.usaloc.alloc_c2[15:0];
release tb_top.cpu.l2t3.usaloc.ua_ecc_c2[6:0];
release tb_top.cpu.l2t3.usaloc.used_c2[15:0];
release tb_top.cpu.l2t3.usaloc.alloc_c2[15:0];
release tb_top.cpu.l2t4.usaloc.ua_ecc_c2[6:0];
release tb_top.cpu.l2t4.usaloc.used_c2[15:0];
release tb_top.cpu.l2t4.usaloc.alloc_c2[15:0];
release tb_top.cpu.l2t5.usaloc.ua_ecc_c2[6:0];
release tb_top.cpu.l2t5.usaloc.used_c2[15:0];
release tb_top.cpu.l2t5.usaloc.alloc_c2[15:0];
release tb_top.cpu.l2t6.usaloc.ua_ecc_c2[6:0];
release tb_top.cpu.l2t6.usaloc.used_c2[15:0];
release tb_top.cpu.l2t6.usaloc.alloc_c2[15:0];
release tb_top.cpu.l2t7.usaloc.ua_ecc_c2[6:0];
release tb_top.cpu.l2t7.usaloc.used_c2[15:0];
release tb_top.cpu.l2t7.usaloc.alloc_c2[15:0];