verif/env/common/verilog/monitors/pcie_intx_mon.v

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// OpenSPARC T2 Processor File: pcie_intx_mon.v
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module pcie_intx_mon() ;

reg pcie_intx_mon_on;

wire int_a_status;
wire int_b_status;
wire int_c_status;
wire int_d_status;

assign int_a_status = tb_top.cpu.dmu.dmc.imu.iss.rds2iss_intx_int_l[0];
assign int_b_status = tb_top.cpu.dmu.dmc.imu.iss.rds2iss_intx_int_l[1];
assign int_c_status = tb_top.cpu.dmu.dmc.imu.iss.rds2iss_intx_int_l[2];
assign int_d_status = tb_top.cpu.dmu.dmc.imu.iss.rds2iss_intx_int_l[3];

initial
begin
  pcie_intx_mon_on = 1'b1;   // Monitor enabled by default
  if($test$plusargs("pcie_intx_mon_off"))
    pcie_intx_mon_on = 1'b0;
end

//--------------------------------------------------------------------
// Int A Assetion/De-assertion
//--------------------------------------------------------------------
always @(int_a_status)
begin
  if(pcie_intx_mon_on == 1'b1)
  begin
     if (int_a_status == 1'b1)
     begin
        `PR_NORMAL("pcie_intx_mon_on",`NORMAL,"PCIE int A deasserted");
     end
     else if (int_a_status == 1'b0)
     begin
        `PR_NORMAL("pcie_intx_mon_on",`NORMAL,"PCIE int A asserted");
     end
  end
end

//--------------------------------------------------------------------
// Int B Assetion/De-assertion
//--------------------------------------------------------------------
always @(int_b_status)
begin
  if(pcie_intx_mon_on == 1'b1)
  begin
     if (int_b_status == 1'b1)
     begin
        `PR_NORMAL("pcie_intx_mon_on",`NORMAL,"PCIE int B deasserted");
     end
     else if (int_b_status == 1'b0)
     begin
        `PR_NORMAL("pcie_intx_mon_on",`NORMAL,"PCIE int B asserted");
     end
  end
end


//--------------------------------------------------------------------
// Int C Assetion/De-assertion
//--------------------------------------------------------------------
always @(int_c_status)
begin
  if(pcie_intx_mon_on == 1'b1)
  begin
     if (int_c_status == 1'b1)
     begin
        `PR_NORMAL("pcie_intx_mon_on",`NORMAL,"PCIE int C deasserted");
     end
     else if (int_c_status == 1'b0)
     begin
        `PR_NORMAL("pcie_intx_mon_on",`NORMAL,"PCIE int C asserted");
     end
  end
end


//--------------------------------------------------------------------
// Int D Assetion/De-assertion
//--------------------------------------------------------------------
always @(int_d_status)
begin
  if(pcie_intx_mon_on == 1'b1)
  begin
     if (int_d_status == 1'b1)
     begin
        `PR_NORMAL("pcie_intx_mon_on",`NORMAL,"PCIE int D deasserted");
     end
     else if (int_d_status == 1'b0)
     begin
        `PR_NORMAL("pcie_intx_mon_on",`NORMAL,"PCIE int D asserted");
     end
  end
end

endmodule