verif/env/common/verilog/soc_sync/fc_niu_csr_probe.v

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//
// OpenSPARC T2 Processor File: fc_niu_csr_probe.v
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`include "fc.vh"
`include "defines.vh"

`define NIU_UCB `CPU.rdp.niu_pio_ucb
`define NIU_PIO `CPU.rdp.niu_pio
`define FM_MAX 12'hfff

module fc_niu_csr_probe;
   reg [26:0] addr[4095:0];
   reg [63:0] data;
   reg [11:0] wrptr;
   reg [11:0] rdptr;

   integer niu_csr;
integer i;

   initial begin
       wrptr = 12'h0;
       rdptr = 12'h0;
   end

   always @ (`NIU_PIO.ucb_rd_req or `NIU_PIO.fifo_wr_en) begin
        if ((`NIU_PIO.ucb_rd_req == 1'b1) && (`NIU_PIO.fifo_wr_en == 1'b1)) begin
            addr[wrptr] = `NIU_PIO.ucb_addr;
            `PR_INFO ("niu_csr_probe", `INFO, "ts=%d addr[%h] gets %h\n", `TOP.core_cycle_cnt-1, wrptr, `NIU_PIO.ucb_addr);
            if (wrptr == `FM_MAX)
               wrptr = 12'h0;
            else
               wrptr = wrptr + 1;
        end
   end


   always @ (posedge `NIU_UCB.rd_ack_vld or posedge `NIU_UCB.rd_nack_vld) begin
        if (wrptr == rdptr) begin
            `PR_ERROR("niu_csr_probe", `ERROR, "A data phase without an address phase received");
        end
        else begin
            data = {`NIU_UCB.data_out[7:0],`NIU_UCB.data_out[15:8],`NIU_UCB.data_out[23:16],`NIU_UCB.data_out[31:24],`NIU_UCB.data_out[39:32],`NIU_UCB.data_out[47:40],`NIU_UCB.data_out[55:48],`NIU_UCB.data_out[63:56]} ;
            `PR_INFO ("niu_csr_probe", `INFO, "ts=%0d NIU CSR READ RETURN:  address %x  data %x ",
                `TOP.core_cycle_cnt-1,  {24'h0, 8'h81, 5'h0, addr[rdptr]}, data);
             if (`PARGS.nas_check_on )
                niu_csr = $sim_send(`PLI_CSR_READ, {24'h0, 8'h81, 5'h0, addr[rdptr]}, data, 8'h01);
             if (rdptr == `FM_MAX)
                rdptr = 12'h0;
             else
                rdptr = rdptr + 1;
        end

   end // always @ (posedge


endmodule // fc_niu_csr_probe