// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: defaults.config
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
#undef VCS_BUILD_WITH_GPP
#define VCS_BUILD_WITH_GPP -LDFLAGS -R -LDFLAGS /import/freetools/local/gcc/3.3.2/lib
#define SUNV_PATH /import/n2-tools/release/sunv/2.88
#define LAVA_LIB_PATH /import/n2-librel/integration/release/rel_2.4
#define T2_LIB_PATH $DV_ROOT/libs
// These 6 lines are obsolete and will be removed. DO NOT USE. See SUNVLIBS_* below.
#define LIBFILE1 OBSOLETE_SEE_DEFAULTS.CONFIG
#define LIBFILE2 OBSOLETE_SEE_DEFAULTS.CONFIG
#define LIBFILE3 OBSOLETE_SEE_DEFAULTS.CONFIG
#define LIBFILE4 OBSOLETE_SEE_DEFAULTS.CONFIG
#define LIBFILE5 OBSOLETE_SEE_DEFAULTS.CONFIG
#define SUNVLIB OBSOLETE_SEE_DEFAULTS.CONFIG
#if defined (GATESIM) || defined (USE_ASIC_GATES) || defined (GATES)
#define SUNVLIBS_SUNV SUNV_PATH/library/cl_rtl_ext.v:LAVA_LIB_PATH/cl_dp1/compiled/cl_dp1.v:LAVA_LIB_PATH/cl_u1/compiled/cl_u1.v:LAVA_LIB_PATH/cl_sc1/compiled/cl_sc1.v:LAVA_LIB_PATH/cl_a1/compiled/cl_a1.v:/import/n2/COMMON_LIB/2.0/libs/common/mc1_l/compiled/cl_mc1.v:LAVA_LIB_PATH/cl_dp1lvt/compiled/cl_dp1lvt.v:LAVA_LIB_PATH/cl_u1lvt/compiled/cl_u1lvt.v:LAVA_LIB_PATH/cl_u1gb/compiled/cl_u1gb.v:LAVA_LIB_PATH/cl_sc1gb/compiled/cl_sc1gb.v:LAVA_LIB_PATH/cl_a1gb/compiled/cl_a1gb.v
#define SUNVLIBS_OTHER -v SUNV_PATH/library/cl_rtl_ext.v -v LAVA_LIB_PATH/cl_dp1/compiled/cl_dp1.v -v LAVA_LIB_PATH/cl_u1/compiled/cl_u1.v -v LAVA_LIB_PATH/cl_sc1/compiled/cl_sc1.v -v LAVA_LIB_PATH/cl_a1/compiled/cl_a1.v -v /import/n2/COMMON_LIB/2.0/libs/common/mc1_l/compiled/cl_mc1.v -v LAVA_LIB_PATH/cl_dp1lvt/compiled/cl_dp1lvt.v -v LAVA_LIB_PATH/cl_u1lvt/compiled/cl_u1lvt.v -v LAVA_LIB_PATH/cl_u1gb/compiled/cl_u1gb.v -v LAVA_LIB_PATH/cl_sc1gb/compiled/cl_sc1gb.v -v LAVA_LIB_PATH/cl_a1gb/compiled/cl_a1gb.v
// #define SUNVLIBS_SUNV SUNV_PATH/library/cl_rtl_ext.v:LAVA_LIB_PATH/cl_dp1/compiled/cl_dp1.v:LAVA_LIB_PATH/cl_u1/compiled/cl_u1.v:LAVA_LIB_PATH/cl_sc1/compiled/cl_sc1.v:LAVA_LIB_PATH/cl_a1/compiled/cl_a1.v:/import/n2/COMMON_LIB/2.0/libs/common/mc1_l/compiled/cl_mc1.v:LAVA_LIB_PATH/cl_a1gb/compiled/cl_a1gb.v
// #define SUNVLIBS_OTHER -v SUNV_PATH/library/cl_rtl_ext.v -v LAVA_LIB_PATH/cl_dp1/compiled/cl_dp1.v -v LAVA_LIB_PATH/cl_u1/compiled/cl_u1.v -v LAVA_LIB_PATH/cl_sc1/compiled/cl_sc1.v -v LAVA_LIB_PATH/cl_a1/compiled/cl_a1.v -v /import/n2/COMMON_LIB/2.0/libs/common/mc1_l/compiled/cl_mc1.v
#define SUNVLIBS_SUNV T2_LIB_PATH/cl/cl_rtl_ext.v:T2_LIB_PATH/cl/cl_dp1/cl_dp1.v:T2_LIB_PATH/cl/cl_u1/cl_u1.v:T2_LIB_PATH/cl/cl_sc1/cl_sc1.v:T2_LIB_PATH/cl/cl_a1/cl_a1.v:T2_LIB_PATH/c1/cl_mc1/cl_mc1.v:T2_LIB_PATH/cl/cl_a1gb/cl_a1gb.v
#define SUNVLIBS_OTHER -v T2_LIB_PATH/cl/cl_rtl_ext.v -v T2_LIB_PATH/cl/cl_dp1/cl_dp1.v -v T2_LIB_PATH/cl/cl_u1/cl_u1.v -v T2_LIB_PATH/cl/cl_sc1/cl_sc1.v -v T2_LIB_PATH/cl/cl_a1/cl_a1.v -v T2_LIB_PATH/cl/cl_mc1/cl_mc1.v
#define SUNVMACROS SUNV_PATH/macros
#define SUNVPERLINC SUNV_PATH/include
// common options to force on entire project
// uplift 200125 to an error; kills Axis
#define SUNVFORCEOPTS -sunv_args=-error=200125
$DV_ROOT/design/ccu/ccu_l/ccu/rtl:\
$DV_ROOT/design/ccx/rtl:\
$DV_ROOT/design/cpu/rtl:\
$DV_ROOT/design/esr/esr_l/esr/rtl:\
$DV_ROOT/design/db0/rtl:\
$DV_ROOT/design/db1/rtl:\
$DV_ROOT/libs/clk/n2_clk_clhdr_cust_l/n2_clk_clhdr_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_gl_cust_l/n2_clk_gl_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_spc_cust_l/n2_clk_spc_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_ccx_cust_l/n2_clk_ccx_cust/rtl:\
$DV_ROOT/libs/analog/n2_core_pll_cust_l/n2_core_pll_cust/rtl:\
$DV_ROOT/libs/analog/n2_esd_vpp_cust_l/n2_esd_vpp_cust/rtl:\
$DV_ROOT/libs/analog/n2_esd_core_cust_l/n2_esd_core_cust/rtl:\
$DV_ROOT/libs/analog/n2_revid_cust_l/n2_revid_cust/rtl:\
$DV_ROOT/libs/analog/n2_rng_cust_l/n2_rng_cust/rtl:\
$DV_ROOT/libs/analog/n2_tmpd_cust_l/n2_tmpd_cust/rtl:\
$DV_ROOT/libs/analog/n2_pcma_cust_l/n2_pcma_cust/rtl:\
$DV_ROOT/libs/analog/n2_pcmb_cust_l/n2_pcmb_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_ccx_cmp_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_mio_cmp_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_mio_io_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_db0_io_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_db0_cmp_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_db1_cmp_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_db1_io_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_l2t_cmp_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_l2b_cmp_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_l2d_cmp_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_sii_cmp_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_sii_io_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_sio_cmp_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_sio_io_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_efu_cmp_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_efu_io_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_rst_cmp_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_rst_io_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_rst_io2x_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_rst_dr_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_ncu_cmp_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_ncu_io_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_dmu_io_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_mcu_cmp_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_mcu_dr_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_mcu_io_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_spc_cmp_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_tcu_cmp_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_tcu_io_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_clkchp_4sel_32x_cust_l/n2_clk_clkchp_4sel_32x_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_clstr_hdr_cust_l/n2_clk_clstr_hdr_cust/rtl:\
$DV_ROOT/libs/clk/n2_clk_clstr_hdr1_cust_l/n2_clk_clstr_hdr1_cust/rtl:\
$DV_ROOT/libs/n2sram/mp/n2_mam_mp_160x66_cust_l/n2_mam_mp_160x66_cust/rtl:\
$DV_ROOT/libs/tisram/core/n2_ict_sp_1920b_cust_l/n2_ict_sp_1920b_cust/rtl:\
$DV_ROOT/libs/tisram/core/n2_icd_sp_16p5kb_cust_l/n2_icd_sp_16p5kb_cust/rtl:\
$DV_ROOT/libs/tisram/core/n2_dta_sp_1920b_cust_l/n2_dta_sp_1920b_cust/rtl:\
$DV_ROOT/libs/tisram/core/n2_dca_sp_9kb_cust_l/n2_dca_sp_9kb_cust/rtl:\
$DV_ROOT/libs/n2sram/mp/n2_frf_mp_256x78_cust_l/n2_frf_mp_256x78_cust/rtl:\
$DV_ROOT/libs/n2sram/mp/n2_irf_mp_128x72_cust_l/n2_irf_mp_128x72_cust/rtl:\
$DV_ROOT/libs/n2sram/dp/n2_dva_dp_32x32_cust_l/n2_dva_dp_32x32_cust/rtl:\
$DV_ROOT/libs/n2sram/dp/n2_arf_dp_16x128_cust_l/n2_arf_dp_16x128_cust/rtl:\
$DV_ROOT/libs/n2sram/cams/n2_stb_cm_64x45_cust_l/n2_stb_cm_64x45_cust/rtl:\
$DV_ROOT/libs/n2sram/tlbs/n2_tlb_tl_128x59_cust_l/n2_tlb_tl_128x59_cust/rtl:\
$DV_ROOT/libs/n2sram/tlbs/n2_tlb_tl_64x59_cust_l/n2_tlb_tl_64x59_cust/rtl:\
$DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_128x42s_cust_l/n2_com_dp_128x42s_cust/rtl:\
$DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x152_cust_l/n2_com_dp_32x152_cust/rtl:\
$DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_64x84_cust_l/n2_com_dp_64x84_cust/rtl:\
$DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x84_cust_l/n2_com_dp_32x84_cust/rtl:\
$DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x72_cust_l/n2_com_dp_32x72_cust/rtl:\
$DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_64x72s_cust_l/n2_com_dp_64x72s_cust/rtl:\
$DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_64x72_cust_l/n2_com_dp_64x72_cust/rtl:\
$DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_16x72_cust_l/n2_com_dp_16x72_cust/rtl:\
$DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_16x132s_cust_l/n2_com_dp_16x132s_cust/rtl:\
$DV_ROOT/libs/clk/n2_flop_bank_cust_l/n2_flop_bank_cust/rtl:\
$DV_ROOT/design/dec/rtl:\
$DV_ROOT/design/dmu/dmu_l/dmu/rtl:\
$DV_ROOT/design/efu/rtl:\
$DV_ROOT/design/rdp/rdp_l/rdp/rtl:\
$DV_ROOT/design/tds/tds_l/tds/rtl:\
$DV_ROOT/design/rtx/rtx_l/rtx/rtl:\
$DV_ROOT/design/mac/mac_l/mac/rtl:\
$DV_ROOT/design/exu/rtl:\
$DV_ROOT/design/fgu/rtl:\
$DV_ROOT/design/gkt/rtl:\
$DV_ROOT/design/ifu/rtl:\
$DV_ROOT/design/l2b/rtl:\
$DV_ROOT/design/l2t/rtl:\
$DV_ROOT/design/lsu/rtl:\
$DV_ROOT/design/mcu/rtl:\
$DV_ROOT/design/fsr/fsr/fsr/rtl:\
$DV_ROOT/design/fsr_left/fsr_left_l/fsr_left/rtl:\
$DV_ROOT/design/fsr_right/fsr_right_l/fsr_right/rtl:\
$DV_ROOT/design/fsr_bottom/fsr_bottom_l/fsr_bottom/rtl:\
$DV_ROOT/design/mio/mio_l/mio/rtl:\
$DV_ROOT/design/niu/niu_mac_l/niu_xmac/rtl:\
$DV_ROOT/design/niu/niu_rxc_l/niu_zcp/rtl:\
$DV_ROOT/design/mmu/rtl:\
$DV_ROOT/design/ncu/rtl:\
$DV_ROOT/design/peu/peu_l/peu/rtl:\
$DV_ROOT/design/psr/psr_l/psr/rtl:\
$DV_ROOT/design/pku/rtl:\
$DV_ROOT/design/pmu/rtl:\
$DV_ROOT/design/sii/rtl:\
$DV_ROOT/design/sio/rtl:\
$DV_ROOT/design/spc/rtl:\
$DV_ROOT/design/spu/rtl:\
$DV_ROOT/design/tcu/rtl:\
$DV_ROOT/design/tlu/rtl:\
$DV_ROOT/design/rst/rtl:\
$DV_ROOT/design/l15/rtl:\
$DV_ROOT/design/lib/rtl:\
$DV_ROOT/libs/io/io_com/io_com_l/n2_io_com_sig_esd/rtl:\
$DV_ROOT/libs/io/io_com/io_com_l/n2_io_com_vdd_esd/rtl:\
$DV_ROOT/libs/n2sram/async/async_l/n2_com_256x132async_dp_cust/rtl:\
$DV_ROOT/libs/n2sram/async/async_l/n2_com_64x132async_dp_cust/rtl:\
$DV_ROOT/libs/n2sram/async/n2_com_256x132async_dp_cust_l/n2_com_256x132async_dp_cust/rtl:\
$DV_ROOT/libs/n2sram/async/n2_com_64x132async_dp_cust_l/n2_com_64x132async_dp_cust/rtl:\
$DV_ROOT/libs/n2sram/async/n2_mcu_32x72async_dp_cust_l/n2_mcu_32x72async_dp_cust/rtl:\
$DV_ROOT/libs/n2sram/cams/cam_1r1w_l/n2_cm_1r1w_adff/rtl:\
$DV_ROOT/libs/n2sram/cams/cam_1r1w_l/n2_cm_1r1w_adffhdr/rtl:\
$DV_ROOT/libs/n2sram/cams/cam_1r1w_l/n2_cm_1r1w_buf_64x/rtl:\
$DV_ROOT/libs/n2sram/cams/cam_1r1w_l/n2_cm_1r1w_dff/rtl:\
$DV_ROOT/libs/n2sram/cams/cam_1r1w_l/n2_cm_1r1w_dff32x/rtl:\
$DV_ROOT/libs/n2sram/cams/cam_1r1w_l/n2_cm_1r1w_dffhdr/rtl:\
$DV_ROOT/libs/n2sram/cams/cam_1r1w_l/n2_cm_1r1w_hdr24x/rtl:\
$DV_ROOT/libs/n2sram/cams/cam_1r1w_l/n2_cm_1r1w_hdr8x/rtl:\
$DV_ROOT/libs/n2sram/cams/cam_1r1w_l/n2_cm_1r1w_hdr8x@sheet001/rtl:\
$DV_ROOT/libs/n2sram/cams/cam_1r1w_l/n2_cm_1r1w_m_byplat_hdr/rtl:\
$DV_ROOT/libs/n2sram/cams/cam_1r1w_l/n2_cm_1r1w_m_latch/rtl:\
$DV_ROOT/libs/n2sram/cams/cam_1r1w_l/n2_cm_1r1w_m_latch_hdr/rtl:\
$DV_ROOT/libs/n2sram/cams/cam_1r1w_l/n2_cm_1r1w_strhdr24x/rtl:\
$DV_ROOT/libs/n2sram/cams/cam_1r1w_l/n2_cm_1r1w_strlow24x/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_32x40_1r1w_l/cp_32x40_read/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_32x40_1r1w_l/cp_32x40_write/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_32x40_1r1w_l/cp_cm_32x40_match/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_32x40_1r1w_l/n2_cm_32x40_1r1w/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_32x40_1r1w_l/n2_cm_32x40_1r1w_aryio/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_32x40_1r1w_l/n2_cm_32x40_1r1w_bottom/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_32x40_1r1w_l/n2_cm_32x40_1r1w_c_en/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_32x40_1r1w_l/n2_cm_32x40_1r1w_io_col/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_32x40_1r1w_l/n2_cm_32x40_1r1w_iom_col/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_32x40_1r1w_l/n2_cm_32x40_1r1w_m_array/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_32x40_1r1w_l/n2_cm_32x40_1r1w_m_array2/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_32x40_1r1w_l/n2_cm_32x40_1r1w_m_io/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_32x40_1r1w_l/n2_cm_32x40_1r1w_m_pre/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_32x40_1r1w_l/n2_cm_32x40_1r1w_m_pre_ary/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_32x40_1r1w_l/n2_cm_32x40_1r1w_r_pre/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_32x40_1r1w_l/n2_cm_32x40_1r1w_rw_en/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_32x40_1r1w_l/n2_cm_32x40_1r1w_rwctl/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_32x40_1r1w_l/n2_cm_32x40_adffary/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_8x40b_1r1w_l/cp_cm_8x40b_match/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_8x40b_1r1w_l/n2_cm_8x40b_1r1w/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_8x40b_1r1w_l/n2_cm_8x40b_1r1w_array/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_8x40b_1r1w_l/n2_cm_8x40b_1r1w_aryio/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_8x40b_1r1w_l/n2_cm_8x40b_1r1w_bottom/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_8x40b_1r1w_l/n2_cm_8x40b_1r1w_c_en/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_8x40b_1r1w_l/n2_cm_8x40b_1r1w_cdvr/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_8x40b_1r1w_l/n2_cm_8x40b_1r1w_iom_col/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_8x40b_1r1w_l/n2_cm_8x40b_1r1w_m_array/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_8x40b_1r1w_l/n2_cm_8x40b_1r1w_m_io/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_8x40b_1r1w_l/n2_cm_8x40b_1r1w_wldrv/rtl:\
$DV_ROOT/libs/n2sram/cams/cm_8x40b_1r1w_l/n2_cm_8x40b_adffary/rtl:\
$DV_ROOT/libs/n2sram/cams/n2_com_32x60_cm_cust_l/n2_com_32x60_cm_cust/rtl:\
$DV_ROOT/libs/n2sram/cams/n2_com_cm_32x40_cust_l/n2_com_cm_32x40_cust/rtl:\
$DV_ROOT/libs/n2sram/cams/n2_com_cm_64x60_cust_l/n2_com_cm_64x60_cust/rtl:\
$DV_ROOT/libs/n2sram/cams/n2_com_cm_64x64_cust_l/n2_com_cm_64x64_cust/rtl:\
$DV_ROOT/libs/n2sram/cams/n2_com_cm_8x40_cust_l/n2_com_cm_8x40_cust/rtl:\
$DV_ROOT/libs/n2sram/cams/n2_mmu_cm_64x34s_cust_l/n2_mmu_cm_64x34s_cust/rtl:\
$DV_ROOT/libs/n2sram/cams/n2_stb_cm_64x45_cust_l/n2_stb_cm_64x45_cust/rtl:\
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$DV_ROOT/libs/tisram/soc/n2_l2d_sp_512kb_cust_l/p_ntran/rtl:\
$DV_ROOT/libs/tisram/soc/n2_l2d_sp_512kb_cust_l/p_ptran/rtl:\
$DV_ROOT/libs/tisram/soc/n2_l2t_sp_28kb_cust_l/n2_l2t_sp_28kb_cust/rtl:\
$DV_ROOT/libs/tisram/sp/n2_dca_sp_9kb_cust_l/n2_dca_sp_9kb_cust/rtl:\
$DV_ROOT/libs/tisram/sp/n2_dta_sp_1920b_cust_l/n2_dta_sp_1920b_cust/rtl:\
$DV_ROOT/libs/tisram/sp/n2_icd_sp_16p5kb_cust_l/n2_icd_sp_16p5kb_cust/rtl:\
$DV_ROOT/libs/tisram/sp/n2_ict_sp_1920b_cust_l/n2_ict_sp_1920b_cust/rtl:\
$DV_ROOT/libs/tisram/sp/n2_l2d_sp_512kb_cust_l/n2_l2d_sp_512kb_cust/rtl:\
$DV_ROOT/libs/tisram/sp/n2_l2t_sp_28kb_cust_l/n2_l2t_sp_28kb_cust/rtl:\
$DV_ROOT/libs/tisram/temp_sram_l/ifu_ftu_icd_cust/rtl:\
$DV_ROOT/libs/tisram/temp_sram_l/ifu_ftu_ict_cust/rtl:\
$DV_ROOT/libs/tisram/temp_sram_l/l2d/rtl:\
$DV_ROOT/libs/tisram/temp_sram_l/lib_r_efa_cust/rtl:\
$DV_ROOT/libs/tisram/temp_sram_l/lsu_dca_cust/rtl:\
$DV_ROOT/libs/tisram/temp_sram_l/lsu_dta_cust/rtl:\
$DV_ROOT/libs/tisram/temp_sram_l/n2_dca_sp_9KB_cust/rtl:\
$DV_ROOT/libs/tisram/temp_sram_l/n2_dct_sp_1920B_cust/rtl:\
$DV_ROOT/libs/tisram/temp_sram_l/n2_efa_sp_256B_cust/rtl:\
$DV_ROOT/libs/tisram/temp_sram_l/n2_icd_sp_16p5kb_cust/rtl:\
$DV_ROOT/libs/tisram/temp_sram_l/n2_ict_sp_1920B_cust/rtl:\
$DV_ROOT/libs/tisram/temp_sram_l/n2_l2d_sp_512kb_cust/rtl:\
$DV_ROOT/libs/tisram/temp_sram_l/n2_l2t_sp_28kb_cust/rtl:\
$DV_ROOT/libs/tisram/temp_sram_l/n2_r_l2t_cust/rtl:\
$DV_ROOT/libs/tisram/temp_sram_l/temp_sram/rtl:\
projects / OpenSPARC-T2-DV / blob