// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: lpr_a.csr_define.vri
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`define FIRE_PLC_TLU_CTB_LPR_A_CSRBUS_EXT_ADDR_WIDTH 13
`define FIRE_PLC_TLU_CTB_LPR_A_CSRBUS_EXT_ADDR_RANGE 12:0
//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB
//-------------------------------------------------------
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_HW_ADDR 27'b000000011011100000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_ADDR 30'b000000011011100000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_NAME "fire_plc_tlu_ctb_lpr_csr_a_ahb"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_WIDTH 64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DEPTH 8192
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_SLC 63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_INT_SLC 63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_ahb"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_LOW_ADDR_WIDTH 13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_SEL_RANGE 12:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_ADDR_RANGE 26:13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_HW_LD_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_INTERNAL_REG 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_EXTERNAL_DECODE_REG 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_ALIASED_FROM 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_ZERO_TIME_OMNI 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_HW_ACC_JTAG_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_HW_ACC_JTAG_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_HW_ACC_PIO_SLOW_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_HW_ACC_PIO_SLOW_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_HW_ACC_PIO_MED_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_HW_ACC_PIO_MED_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_HW_ACC_PIO_FAST_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_HW_ACC_PIO_FAST_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_NUM_FIELDS 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DATA_FID 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DATA_SLC 31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DATA_WIDTH 32
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DATA_INT_SLC 31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DATA_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DATA_FMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DATA_HW_LD_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DATA_POR_VALUE 32'b00000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DATA_FIELD_NAME "data"
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