verif/env/niu/vera/niu_pio/include/fflp_defines.vri

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: fflp_defines.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
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// otherwise unspecified.
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// have any questions.
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// ========== Copyright Header End ============================================
#ifdef VEGA_CHIP_LEVEL
  #ifdef BH_BOARD_LEVEL
    #define TESTBENCH_TOP    "BH_board
    #define FFLP_DUV_PATH    "BH_board.vega.vega.ffl_blk
    #define BMC_FULL_CTRL    "BH_board
    #define CAM_DUV_PATH     "BH_board.cam_conn.cam_ram.IPC
    #define ZBTRAM_DUV_PATH  "BH_board.cam_conn.zbtram.ZBT_SRAM
  #else
    #ifdef DFTGATE_SIM
       #define TESTBENCH_TOP    "vega_tb_top
       #define FFLP_DUV_PATH    "vega_tb_top.vega_asic_top.ffl_blk.coreInstance
       #define BMC_FULL_CTRL    "vega_tb_top
       #define CAM_DUV_PATH     "vega_tb_top.cam_ram.IPC
       #define ZBTRAM_DUV_PATH  "vega_tb_top.cam_ram.ZBT_SRAM
    #else
       #define TESTBENCH_TOP    "vega_tb_top
       #define FFLP_DUV_PATH    "vega_tb_top.vega_asic_top.ffl_blk
       #define BMC_FULL_CTRL    "vega_tb_top
       #define CAM_DUV_PATH     "vega_tb_top.cam_ram.IPC
       #define ZBTRAM_DUV_PATH  "vega_tb_top.cam_ram.ZBT_SRAM
    #endif
  #endif
#else
  #ifdef DFTGATE_SIM
    #define TESTBENCH_TOP     "fflp_testbench
    #define FFLP_DUV_PATH     "fflp_testbench.ffl_top
    #define FFLP_DUV_PATH_DFT "fflp_testbench.ffl_top.coreInstance
    #define BMC_FULL_CTRL     "fflp_testbench
    #define CAM_DUV_PATH      "fflp_testbench.cam_ram.IPC
    #define ZBTRAM_DUV_PATH   "fflp_testbench.cam_ram.ZBT_SRAM
  #else
    #define TESTBENCH_TOP     "fflp_testbench
    #define FFLP_DUV_PATH     "fflp_testbench.ffl_top
    #define FFLP_DUV_PATH_DFT "fflp_testbench.ffl_top
    #define BMC_FULL_CTRL     "fflp_testbench
    #define CAM_DUV_PATH      "fflp_testbench.cam_ram.IPC
    #define ZBTRAM_DUV_PATH   "fflp_testbench.cam_ram.ZBT_SRAM
  #endif
#endif

//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
//@@ These are the FFLP defines which will be edited @@
//@@ in vera_defines.vrh file                        @@
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

#define OC192_MODE          1'b1

#define ARP_FRAME_TYPE     16'h0806
#define RARP_FRAME_TYPE    16'h8035
#define IPV4_FRAME         16'h0800
#define IPV6_FRAME         16'h86dd
/*
#define NO_IP_FRAME_TYPE    5'bxxx0x
#define IPV4_FRAME_TYPE     5'b00010
#define IPV4_TAGGED         5'b00110
#define IPV4_LLC            5'b00011
#define IPV4_TAGGED_LLC     5'b00111
#define IPV6_FRAME_TYPE     5'b01010
#define IPV6_TAGGED         5'b01110
#define IPV6_LLC            5'b01011
#define IPV6_TAGGED_LLC     5'b01111
#define TUNNEL_FRAME        5'b1xxxx
*/
#define NO_IP_FRAME_TYPE    5'b0xx0x
#define IPV4_FRAME_TYPE     5'b00010
#define IPV4_TAGGED         5'b00110
#define IPV4_LLC            5'b00011
#define IPV4_TAGGED_LLC     5'b00111
#define IPV6_FRAME_TYPE     5'b01010
#define IPV6_TAGGED         5'b01110
#define IPV6_LLC            5'b01011
#define IPV6_TAGGED_LLC     5'b01111
//#define TUNNEL_FRAME        6'bx1xxxx
#define USER_FRAME_TYPE     5'b10000
#define USER_TAGGED         5'b10100
#define USER_LLC            5'b10001
#define USER_TAGGED_LLC     5'b10101

//#define NO_IP_TYPE          4'h0
//#define IPV4_TYPE           4'h4
//#define IPV6_TYPE           4'h6
#define VER_IPV4            4'h4
#define VER_IPV6            4'h6
#define PROTOCOL_TCP        8'h06
#define PROTOCOL_SCTP       8'h84
#define NEXT_HDR_TCP        8'h06
#define NEXT_HDR_SCTP       8'h84
#define PROTOCOL_UDP        8'h11
#define NEXT_HDR_UDP        8'h11
#define PROTOCOL_IPSEC_ESP  8'h32
#define PROTOCOL_IPSEC_AH   8'h33
#define NEXT_HDR_IPSEC_ESP  8'h32
#define NEXT_HDR_IPSEC_AH   8'h33
#define CAM_ENTRIES         256

//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
//@@ Hardwire Class and Mask values.                 @@
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

#define  CLASS8_HDR   122'h0000_0600_0000_0000_0000_0045_0800 //TCP/IPv4
#define  CLASS9_HDR   122'h0000_1100_0000_0000_0000_0045_0800 //UDP/IPv4
#define  CLASS10_HDR  122'h0000_3200_0000_0000_0000_0045_0800 //SEC/IPv4
#define  CLASS11_HDR  122'h0000_0000_0006_0000_0000_0060_08dd //TCP/IPv6
#define  CLASS12_HDR  122'h0000_0000_0011_0000_0000_0060_08dd //UDP/IPv6
#define  CLASS13_HDR  122'h0000_0000_0032_0000_0000_0060_08dd //SEC/IPv6
#define  CLASS14_HDR  122'h0000_0000_0000_0000_0000_0000_0806 //ARP
#define  CLASS15_HDR  122'h0000_0000_0000_0000_0000_0000_0835 //RARP

#define  CLASS8_BIT_MASK_HDR   112'h0000_ff00_0000_0000_0000_00ff_ffff
#define  CLASS9_BIT_MASK_HDR   112'h0000_ff00_0000_0000_0000_00ff_ffff
#define  CLASS10_BIT_MASK_HDR  112'h0000_fe00_0000_0000_0000_00ff_ffff
#define  CLASS11_BIT_MASK_HDR  112'h0000_0000_00ff_0000_0000_00f0_ffff
#define  CLASS12_BIT_MASK_HDR  112'h0000_0000_00ff_0000_0000_00f0_ffff
#define  CLASS13_BIT_MASK_HDR  112'h0000_0000_00fe_0000_0000_00f0_ffff
#define  CLASS14_BIT_MASK_HDR  112'h0000_0000_0000_0000_0000_0000_ffff
#define  CLASS15_BIT_MASK_HDR  112'h0000_0000_0000_0000_0000_0000_ffff

#define  CLASS8_BYTE_MASK_HDR   28'b0000_0100_0000_0000_0000_0001_0101
#define  CLASS9_BYTE_MASK_HDR   28'b0000_0100_0000_0000_0000_0001_0101
#define  CLASS10_BYTE_MASK_HDR  28'b0000_1100_0000_0000_0000_0001_0101
#define  CLASS11_BYTE_MASK_HDR  28'b0000_0000_0001_0000_0000_0011_0101
#define  CLASS12_BYTE_MASK_HDR  28'b0000_0000_0001_0000_0000_0011_0101
#define  CLASS13_BYTE_MASK_HDR  28'b0000_0000_0011_0000_0000_0011_0101
#define  CLASS14_BYTE_MASK_HDR  28'b0000_0000_0000_0000_0000_0000_0101
#define  CLASS15_BYTE_MASK_HDR  28'b0000_0000_0000_0000_0000_0000_0101

#define  CLASS_0   0
#define  CLASS_1   1
#define  CLASS_2   2
#define  CLASS_3   3
#define  CLASS_4   4
#define  CLASS_5   5
#define  CLASS_6   6
#define  CLASS_7   7
#define  CLASS_8   8
#define  CLASS_9   9
#define  CLASS_10  10
#define  CLASS_11  11
#define  CLASS_12  12
#define  CLASS_13  13
#define  CLASS_14  14
#define  CLASS_15  15
#define  CLASS_16  16
#define  CLASS_17  17
#define  CLASS_18  18
#define  CLASS_19  19
#define  CLASS_20  20
#define  CLASS_21  21
#define  CLASS_22  22
#define  CLASS_23  23

// CAM CMD Bus Defines
//cam instructions, insn[16:0] with crb[2:0] tied to 0s.
//                      gmask[16:11], segsel[10:7], ltin[6:4], inst=[3:0]

#define SRCH_CMD                17'b1_0000_0000_0001_0010 //10012
#define SRCH_WIDE_CMD           17'b1_0010_0000_1010_0010 //120a2
#define SRCH_SEC_CMD            17'b1_0001_0000_0001_0010 //11012
#define SRCH_WIDE_SEC_CMD       17'b1_0100_0000_1010_0010 //140a2
#define NFA_LOOKUP_CMD          17'b0_0000_0001_0001_1010 //0011a
#define NFA_WIDE_LOOKUP_CMD     17'b0_0000_0001_1010_1010 //001aa
#define RD_CMD                  17'b0_0000_0000_0000_0000 //00000
#define WR_CMD                  17'b0_0000_0000_0000_0001 //00001
#define RD_SRAM_CMD             17'b0_0000_0000_0000_0100 //00004
#define MOVE_CMD                17'b0_0000_0000_0000_0111 //00007


// CAM Instruction
#define INST_READ           4'b0000
#define CAM_READ            4'b0000
#define LMASK_READ          4'b0000
#define REG_READ            4'b0000
#define ZBTSRAM_READ        4'b0100
#define PARITY              4'b0000
#define MOVE_ENT            4'b0111
#define NFA_LOOKUP          4'b0000

#define INST_WRITE          4'b0001
#define CAM_WRITE           4'b0000
#define LMASK_WRITE         4'b0000
#define REG_WRITE           4'b0000
#define ZBTSRAM_WRITE       4'b0000

#define INST_LOOKUP         4'b0010
#define INST_SRAM_NOW_READ  4'b0000
#define INST_PARITY         4'b0000
#define INST_NFA_LOOKUP     4'b1010

// CAM Instruction Access Type
#define WRITE_CAM_KEY       4'b0001
#define WRITE_CAM_LMASK     4'b0001
#define WRITE_ZBTSRAM       4'b0001
#define WRITE_CAM_REG       4'b0001

// CAM CMDs Defines In CAM_CAM_REG
#define         NOP_CMD                 5'b01000
#define         RD_CAM_REG              5'b01001
#define         WR_CAM_REG              5'b01010
#define         RD_CAM_KEY              5'b01011
#define         WR_CAM_KEY              5'b01100
#define         RD_CAM_LMASK            5'b01101
#define         WR_CAM_LMASK            5'b01110
#define         RD_ASSOC_D              5'b01111
#define         RD_ASSOC_D_W_KEY        5'b10000
#define         WR_ASSOC_D              5'b10001
#define         WR_ASSOC_D_W_KEY        5'b10010
#define         SET_AGE_BIT             5'b10011
#define         UPDATE_BACKLOG          5'b10100
#define         INC_BACKLOG             5'b10101
#define         DEC_BACKLOG             5'b10110
#define         INV_ENTRY               5'b10111
#define         INV_ENTRY_WR_DEF_LMASK  5'b11000
#define         INV_ALL                 5'b11001
#define         MOVE_ENTRY              5'b11010

// CAM Lookup Type
#define LOOKUP_144          3'b001
#define LOOKUP_288          3'b010

// CAM Region Setup
//#define REGION1_144_MAX_INDEX 16'h67ff // the last entry pointer
//#define REGION2_144_MAX_INDEX 16'h7fff // the last entry pointer
//#define REGION1_288_MAX_INDEX 16'he7f8 // the last entry pointer
//#define REGION2_288_MAX_INDEX 16'hfffc // the last entry pointer

// CAM Region Setup
#define REGION1_144_1ST_CAM_INDEX  16'h0    // region1(fflp) 1st  144 entry pointer
#define REGION1_144_LAST_CAM_INDEX 16'h67ff // region1(fflp) 1st  144 entry pointer
#define REGION2_144_1ST_CAM_INDEX  16'h6800 // region2(cpu)  1st  144 entry pointer
#define REGION2_144_LAST_CAM_INDEX 16'h7fff // region2(cpu)  last 144 entry pointer

#define REGION1_288_1ST_CAM_INDEX  16'h8000 // region1(fflp) 1st  288 entry pointer
#define REGION1_288_LAST_CAM_INDEX 16'he7f8 // region1(fflp) 1st  288 entry pointer
#define REGION2_288_1ST_CAM_INDEX  16'he7fc // region2(cpu)  1st  288 entry pointer
#define REGION2_288_LAST_CAM_INDEX 16'hffff // region2(cpu)  last 288 entry pointer

//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
//@ TCP/UDP Related Defines
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
#define SYNC                  1'b1

#define TCP_SYN               2'b00
#define TCP_FLAG              2'b01
#define TCP_FIN               2'b10

#define MAX_LOOKUP_INST_WAIT  1000   // number of clk2x to expect a cam cmd before timeout
#define ZZ                    1000   // number of clk2x to expect a cam cmd before timeout
#define YY                    500    // In normal mode: number of core_clk to expect a fwd_dec before timeout
#define FWD_DEC_TIMEOUT       500    // In normal mode: number of core_clk to expect a fwd_dec before timeout
#define BYBY                  500    // In bypass mode: number of core_clk to expect a fwd_dec before timeout
#define LB_TIMER              1000   // number of cam_clk to expect lb transaction by fflp
#define BAD                   1'b1
#define MAX_WAIT              1000
#define FFLP_BMC_W            1000   // number of cclk  to expect fflp_bmc rd1_addr1 transaction
#define FFLP_BMC_RD1_ADDR2_W  1000   // number of cclk  to expect fflp_bmc rd1_addr2 transaction
#define FFLP_BMC_RD_LATENCY   1000   // number of cclk  to expect data0/1 passed by bmc to fflp
#define FFLP_BMC_WR1_DATA_W   1000   // number of cclk  to expect fflp_bmc wrt transaction

#define BMC_CAM               1000   // number of cclk  to expect fflp_cam transaction
                                     // for lb table as_data update

//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
//@ VLAN TABLE      Defines
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
#define VLAN_BLOCK0           2'b00 // VLAN Table Block0
#define VLAN_BLOCK1           2'b01 // VLAN Table Block1
#define VLAN_BLOCK2           2'b10 // VLAN Table Block2
#define VLAN_BLOCK3           2'b11 // VLAN Table Block3


   #define IP_DB_ENTRIES 128

#define CAM_COMP_ONLY_CLS_CODE  200'hf8_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000
#define CAM_NO_LMASK            200'hff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff
#define CAM_LMASK_CLS_CODE      200'h07_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff
#define CAM_LMASK_L2RDC         200'hff_07ff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff
#define CAM_LMASK_NOPORT        200'hff_fbff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff
#define CAM_LMASK_L4PT_TOS      200'hff_ffff_ffff_ffff_ffff_ffff_00ff_ffff_ffff_ffff_ffff_ffff_ffff
#define CAM_LMASK_L4PT_PID      200'hff_ffff_ffff_ffff_ffff_ffff_ff00_ffff_ffff_ffff_ffff_ffff_ffff
#define CAM_LMASK_L4PT_SPI      200'hff_ffff_ffff_ffff_ffff_ffff_ffff_0000_0000_ffff_ffff_ffff_ffff
#define CAM_LMASK_IPV4_SRC_ADDR 200'hff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_0000_0000_ffff_ffff
#define CAM_LMASK_IPV4_DST_ADDR 200'hff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_0000_0000
#define CAM_LMASK_IPV6_ADDR     200'hff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_0000_0000_0000_0000
#define CAM_LMASK_FRAGMENT_PKTS 200'hf8_0400_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000

#define FLOW_KEY_WIDTH_SIZE     384
#define H1_CRC_32C_POLY         32'h1edc_6f41
#define H2_CRC_CCITT_POLY       16'h1021
#define DEFAULT_HASH1_INITIAL_VALUE 32'hc000_0000