// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: ccu.port.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
//---clock port: each signal is a VERA CLOCK---
//---WARN:: does not contain all CCU ports---
sys_clk; // warn: rtl signal is pll_sys_clk_p
//---reset/mode signals---
//----monitor port: all CCU ports, except UCB signals (ie. ncu_ccu_* and ccu_ncu_*)---
//----WARN: UCB signals defined in ucb.*.vri---
//---the rest: in alphabetical order---
//---ccu internal signals---
//---- Port for sigs that are clocked by IO clock---
port CCU_mon_ioclk_port {
//--- sigs in csr block----
//---- Port for internal signals needed for ccu and clocking verification ----
//---- WARN: these ports/signals are NOT in ccu block ---
port CCU_clks_internal_port {
l2clk; // l2clk of RST block. WARN: cannot use 'rst_l2clk' which is vera interface defined in rst.if.vri
rst_ccu_cmp_sys_sync_en; // inside RST block
rst_ccu_cmp_sys_sync_en3; // inside RST block
rst_ccu_sys_cmp_sync_en; // inside RST block
rst_ccu_sys_cmp_sync_en3; // inside RST block