verif/env/tcu/vera/include/rst.port.vri

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: rst.port.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
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// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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// ========== Copyright Header End ============================================
#ifndef INC_RST_PORT_VRI
#define INC_RST_PORT_VRI

#include "tcu_top_defines.vri"

port sc__port {
  clk;
  por_in_;
  por_;
  pb_xir_;
  pb_rst_;
}

port rst__port {
  clk;
  clk_l2clk;
  clk_iol2clk;
  tb_clk_stop_all;
  tb_clk_stop_one;
  rst_niu_wmr_;
  rst_ncu_unpark_thread;
  rst_ncu_xir_;
  ccu_rst_change;
  tcu_bisx_done;
  tcu_rst_efu_done;
  tcu_pce_ov;
  tcu_rst_io_clk_stop;
  ncu_rst_xir_done;
  rst_mcu_selfrsh;
  tcu_rst_flush_init_ack;
  tcu_rst_flush_stop_ack;
  rst_tcu_flush_init_req;
  rst_tcu_flush_stop_req;
  rst_tcu_asicflush_stop_req;
  tcu_rst_asicflush_stop_ack;

  rst_l2_por_;
  rst_l2_wmr_;
  rst_wmr_protect;
  rst_dmu_peu_por_;
  rst_dmu_peu_wmr_;
  ccu_rst_sync_stable;
  tcu_rst_scan_mode;

  l2t0_rst_fatal_error;
  l2t1_rst_fatal_error;
  l2t2_rst_fatal_error;
  l2t3_rst_fatal_error;
  l2t4_rst_fatal_error;
  l2t5_rst_fatal_error;
  l2t6_rst_fatal_error;
  l2t7_rst_fatal_error;
  ncu_rst_fatal_error;
}

#endif