verif/model/sun/sun_amb.flist

// ========== Copyright Header Begin ==========================================
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// OpenSPARC T2 Processor File: sun_amb.flist
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../verilog/mem/fbdimm/design/global.h
../verilog/mem/fbdimm/design/fbdimm.v
-v ../verilog/mem/fbdimm/design/fbdimm_clk_gen.v
-v ../verilog/mem/fbdimm/design/amb_top.v
-v ../verilog/mem/fbdimm/design/amb_init.v
-v ../verilog/mem/fbdimm/design/ddr_io.v
-v ../verilog/mem/fbdimm/design/crc.v
-v ../verilog/mem/fbdimm/design/voting_logic.v
-v ../verilog/mem/fbdimm/design/training_sequence_fsm.v
-v ../verilog/mem/fbdimm/design/dtm_training.v
-v ../verilog/mem/fbdimm/design/testing_state_fsm.v
-v ../verilog/mem/fbdimm/design/send_ts0.v
-v ../verilog/mem/fbdimm/design/sb_decode_crc.v
-v ../verilog/mem/fbdimm/design/polling_state_fsm.v
-v ../verilog/mem/fbdimm/design/nb_bit_lane_deskew.v
-v ../verilog/mem/fbdimm/design/nb_encode_crc.v
-v ../verilog/mem/fbdimm/design/nb_crc_error_injector.v
-v ../verilog/mem/fbdimm/design/sb_crc_error_injector.v
-v ../verilog/mem/fbdimm/design/idle_lfsr.v
-v ../verilog/mem/fbdimm/design/alert_lfsr.v
-v ../verilog/mem/fbdimm/design/config_state_fsm.v
-v ../verilog/mem/fbdimm/design/channel_mon.v
-v ../verilog/mem/fbdimm/design/fbdimm_nb_fsr.v
-v ../verilog/mem/fbdimm/design/fbdimm_sb_fsr.v
-v ../verilog/mem/fbdimm/library/delay.v
-v ../verilog/mem/fbdimm/library/library.v
-v ../verilog/mem/fbdimm/library/fifo/fifo.v
-v ../verilog/mem/fbdimm/library/fifo/rptr_empty.v
-v ../verilog/mem/fbdimm/library/fifo/sync_w2r.v
-v ../verilog/mem/fbdimm/library/fifo/fifomem.v
-v ../verilog/mem/fbdimm/library/fifo/sync_r2w.v
-v ../verilog/mem/fbdimm/library/fifo/wptr_full.v