//////////////////////////////////////////////////////////////////////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// Projects compatibility: ////
//// 16550D uart (mostly supported) ////
//// Overview (main Features): ////
//// UART core top level. ////
//// Known problems (limits): ////
//// Note that transmitter and receiver instances are inside ////
//// the uart_regs.v file. ////
//// Nothing so far. ////
//// - gorban@opencores.org ////
//// - Igor Mohor (igorm@opencores.org) ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//////////////////////////////////////////////////////////////////////
//// Copyright (C) 2000, 2001 Authors ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//////////////////////////////////////////////////////////////////////
// Revision 1.19 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
// Revision 1.18 2002/07/22 23:02:23 gorban
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
// Revision 1.17 2001/12/19 08:40:03 mohor
// Warnings fixed (unused signals removed).
// Revision 1.16 2001/12/06 14:51:04 gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
// Revision 1.15 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
// Revision 1.14 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
// Revision 1.13 2001/10/20 09:58:40 gorban
// Revision 1.12 2001/08/25 15:46:19 gorban
// Modified port names again
// Revision 1.11 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
// Revision 1.10 2001/08/23 16:05:05 mohor
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
// Revision 1.4 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
// Revision 1.3 2001/05/21 19:12:02 gorban
// Corrected some Linter messages.
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
// Revision 1.0 2001-05-17 21:27:12+02 jacob
module uart_top(wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i,
wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i, int_o, stx_pad_o, srx_pad_i,
rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i, baud_o)
parameter uart_data_width = 8;
parameter uart_addr_width = 3;
input [(uart_addr_width - 1):0]
input [(uart_data_width - 1):0]
output [(uart_data_width - 1):0]
wire [(uart_addr_width - 1):0]
.wb_adr_int (wb_adr_int),
.modem_inputs ({cts_pad_i, dsr_pad_i,
$display("(%m) UART INFO: Data bus width is 8. No Debug interface.\n")
$display("(%m) UART INFO: Has baudrate output\n");