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// OpenSPARC T2 Processor File: dmu_diu_idr.v
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// TMU's DIM - DIU Interface
// CLU's CTM - DIU Interface
idr2mux_dma_pio_data_out,
//////////////////////////////////////////////////////////////////////
//************************* Parameters *************************
//////////////////////////////////////////////////////////////////////
parameter MEM_WIDTH = `FIRE_DLC_TRD_DATA_WDTH+`FIRE_DLC_TRD_BMASK_WDTH+`FIRE_DLC_TRD_DPAR_WDTH;
// parameter MEM_TIEHIGH = 1'b1;
// parameter MEM_TIELOW = 1'b0;
//////////////////////////////////////////////////////////////////////
//************************* Port Declarations *******************
//////////////////////////////////////////////////////////////////////
input tcu_se_scancollar_in;
input tcu_array_wr_inhibit;
// TMU's DIM - DIU Interface
input [`FIRE_DLC_TRD_ADDR_WDTH-1:0] tm2di_addr; // Address width, to address 128 entries DMA / 64 entries PIO 1 bit select
input [`FIRE_DLC_TRD_DATA_WDTH-1:0] tm2di_data; // Data width, 16 bytes
input [`FIRE_DLC_TRD_BMASK_WDTH-1:0] tm2di_bmask; // 16 bit bmask
input [`FIRE_DLC_TRD_DPAR_WDTH-1:0] tm2di_dpar; // Parity width 32 bit parity on data 1 bit for 16 bit bmask
// CLU's CTM - DIU Interface
input [`FIRE_DLC_CRD_ADDR_WDTH-2:0] cl2idr_addr; // Address width, to address 128 entries DMA / 64 entries PIO / 16 entries INT 2 bit select
input cl2di_rd_en; // rd enable for diu ram for n2 power savings BP 5-12-05
// DIU's PDR - CLU's CTM (128 + 16 + 5 = 149)
output [MEM_WIDTH-1:0] idr2mux_dma_pio_data_out; // RAM data output
input [7:0] dmu_mb0_addr;
input [7:0] dmu_mb0_wdata;
//////////////////////////////////////////////////////////////////////
//*************** Submodule Instantiations ***********************
//////////////////////////////////////////////////////////////////////
/* #0in memory_access -read_addr cl2idr_addr -read (!tm2di_wr) -write_addr tm2di_addr -write tm2di_wr
-single_write -read_data idr2mux_dma_pio_data_out -write_data ({tm2di_dpar, tm2di_bmask, tm2di_data}) */
// Checks that any data written on waddr is read on raddr before it is overwritten. In
// addition, it checks that the data read from the memory is correct. Also checks that
// no location is read by raddr and written by waddr in the same cycle.
fire_dlc_ram192x149_211hd4 ram192x149_211hd4
.dib ({tm2di_dpar, tm2di_bmask, tm2di_data}),
.doa (idr2mux_dma_pio_data_out),
//BP N2 9-21-04 add the scan bypass mux
// note: that {tm2di_dpar, tm2di_bmask, tm2di_data} come directly from flops in dmu_tmu_dim_datapath.v
wire [MEM_WIDTH-1:0] dma_pio_data_out;
assign idr2mux_dma_pio_data_out = tcu_array_bypass ? {tm2di_dpar, tm2di_bmask, tm2di_data} : dma_pio_data_out;
//SV 02/24/05 added BIST logic
wire [7:0] rd_addr_ram, wr_addr_ram ;
wire wr_en_ram, rd_en_ram ;
assign din_ram = dmu_mb0_run ? ({dmu_mb0_wdata[4:0],{18{dmu_mb0_wdata}}}) : ({tm2di_dpar, tm2di_bmask, tm2di_data}) ;
assign rd_addr_ram = dmu_mb0_run ? dmu_mb0_addr[7:0] : cl2idr_addr ;
assign wr_addr_ram = dmu_mb0_run ? dmu_mb0_addr[7:0] : tm2di_addr ;
assign wr_en_ram = dmu_mb0_run ? dmu_mb0_diu_wr_en : tm2di_wr ;
assign rd_en_ram = dmu_mb0_run ? dmu_mb0_diu_rd_en : cl2di_rd_en ;
//BP n2 6-16-04 new ram model
// /* 0in memory_access -read_addr cl2idr_addr -read (cl2idr_addr != tm2di_addr)
/* 0in memory_access -read_addr cl2idr_addr -read (cl2di_rd_en & (cl2idr_addr != tm2di_addr) )
-latency 1 -write tm2di_wr
-read_data dma_pio_data_out -write_data ({tm2di_dpar, tm2di_bmask, tm2di_data}) -group mbist_mode */
// Checks that any data written on waddr is read on raddr before it is overwritten. In
// addition, it checks that the data read from the memory is correct. Also checks that
// no location is read by raddr and written by waddr in the same cycle.
n2_dmu_dp_144x149s_cust diu_dma_ram144x149
.dout (dma_pio_data_out),
.tcu_scan_en (tcu_scan_en),
.tcu_se_scancollar_in (tcu_se_scancollar_in),
.tcu_array_wr_inhibit (tcu_array_wr_inhibit),
.tcu_pce_ov (tcu_pce_ov),