design/sys/iop/dmu/rtl/dmu_ilu_cib_defines.h

/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: dmu_ilu_cib_defines.h
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
* available with the language indicating that GPLv2 or any later version
* may be used, or where a choice of which version of the GPL is applied is
* otherwise unspecified.
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
* CA 95054 USA or visit www.sun.com if you need additional information or
* have any questions.
*
*
* ========== Copyright Header End ============================================
*/
`ifdef FIRE_DLC_ILU_CIB_DEFINES
`else
`define FIRE_DLC_ILU_CIB_DEFINES

`define FIRE_DLC_ILU_CIB_INSTANCE_ID_VALUE_A 1'h0
`define FIRE_DLC_ILU_CIB_INSTANCE_ID_VALUE_B 1'h1

//-------------------------------------------------------
//----- Variable definitions for register dmu_ilu_cib_csr_ilu_log_en
//-------------------------------------------------------

`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_HW_ADDR       27'b000000011001010001000000000
`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_ADDR  30'b000000011001010001000000000000
`define FIRE_DLC_ILU_CIB_CSR_B_ILU_LOG_EN_HW_ADDR       27'b000000011101010001000000000
`define FIRE_DLC_ILU_CIB_CSR_B_ILU_LOG_EN_ADDR  30'b000000011101010001000000000000

`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_WIDTH   64
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_DEPTH   1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SLC     63:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_INT_SLC 63:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_POSITION        0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_LOW_ADDR_WIDTH  0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_ADDR_RANGE      26:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_READ_MASK       64'b0000000000000000000000000000000000000000000000000000000011110000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_READ_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_WRITE_MASK      64'b0000000000000000000000000000000000000000000000000000000011110000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SET_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_CLEAR_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_TOGGLE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_RMASK   64'b0000000000000000000000000000000000000000000000000000000011110000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_RESERVED_BIT_MASK       64'b1111111111111111111111111111111111111111111111111111111100001111
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_POR_VALUE       64'b0000000000000000000000000000000000000000000000000000000011110000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_INTERNAL_REG    1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_ZERO_TIME_OMNI  1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_NUM_FIELDS      4
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE3_FID      0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE3_SLC      7:7
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE3_WIDTH    1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE3_INT_SLC  0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE3_POSITION 7
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE3_FMASK    64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE3_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE3_POR_VALUE        1'b1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE2_FID      1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE2_SLC      6:6
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE2_WIDTH    1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE2_INT_SLC  0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE2_POSITION 6
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE2_FMASK    64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE2_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE2_POR_VALUE        1'b1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE1_FID      2
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE1_SLC      5:5
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE1_WIDTH    1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE1_INT_SLC  0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE1_POSITION 5
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE1_FMASK    64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE1_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE1_POR_VALUE        1'b1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_IHB_PE_FID      3
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_IHB_PE_SLC      4:4
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_IHB_PE_WIDTH    1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_IHB_PE_INT_SLC  0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_IHB_PE_POSITION 4
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_IHB_PE_FMASK    64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_IHB_PE_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_IHB_PE_POR_VALUE        1'b1

//-------------------------------------------------------
//----- Variable definitions for register dmu_ilu_cib_csr_ilu_int_en
//-------------------------------------------------------

`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_HW_ADDR       27'b000000011001010001000000001
`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_ADDR  30'b000000011001010001000000001000
`define FIRE_DLC_ILU_CIB_CSR_B_ILU_INT_EN_HW_ADDR       27'b000000011101010001000000001
`define FIRE_DLC_ILU_CIB_CSR_B_ILU_INT_EN_ADDR  30'b000000011101010001000000001000

`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_WIDTH   64
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_DEPTH   1
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SLC     63:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_INT_SLC 63:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_POSITION        0
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_LOW_ADDR_WIDTH  0
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_ADDR_RANGE      26:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_READ_MASK       64'b0000000000000000000000001111000000000000000000000000000011110000
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_READ_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_WRITE_MASK      64'b0000000000000000000000001111000000000000000000000000000011110000
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SET_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_CLEAR_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_TOGGLE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_RMASK   64'b0000000000000000000000001111000000000000000000000000000011110000
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_RESERVED_BIT_MASK       64'b1111111111111111111111110000111111111111111111111111111100001111
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_POR_VALUE       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_INTERNAL_REG    1
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_ZERO_TIME_OMNI  1
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_NUM_FIELDS      8
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_S_FID    0
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_S_SLC    39:39
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_S_WIDTH  1
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_S_INT_SLC        0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_S_POSITION       39
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_S_FMASK  64'b0000000000000000000000001000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_S_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_S_POR_VALUE      1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_S_FID    1
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_S_SLC    38:38
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_S_WIDTH  1
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_S_INT_SLC        0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_S_POSITION       38
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_S_FMASK  64'b0000000000000000000000000100000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_S_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_S_POR_VALUE      1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_S_FID    2
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_S_SLC    37:37
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_S_WIDTH  1
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_S_INT_SLC        0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_S_POSITION       37
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_S_FMASK  64'b0000000000000000000000000010000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_S_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_S_POR_VALUE      1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_S_FID    3
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_S_SLC    36:36
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_S_WIDTH  1
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_S_INT_SLC        0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_S_POSITION       36
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_S_FMASK  64'b0000000000000000000000000001000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_S_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_S_POR_VALUE      1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_P_FID    4
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_P_SLC    7:7
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_P_WIDTH  1
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_P_INT_SLC        0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_P_POSITION       7
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_P_FMASK  64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_P_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_P_POR_VALUE      1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_P_FID    5
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_P_SLC    6:6
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_P_WIDTH  1
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_P_INT_SLC        0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_P_POSITION       6
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_P_FMASK  64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_P_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_P_POR_VALUE      1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_P_FID    6
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_P_SLC    5:5
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_P_WIDTH  1
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_P_INT_SLC        0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_P_POSITION       5
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_P_FMASK  64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_P_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_P_POR_VALUE      1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_P_FID    7
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_P_SLC    4:4
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_P_WIDTH  1
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_P_INT_SLC        0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_P_POSITION       4
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_P_FMASK  64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_P_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_P_POR_VALUE      1'b0

//-------------------------------------------------------
//----- Variable definitions for register dmu_ilu_cib_csr_ilu_en_err
//-------------------------------------------------------

`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_HW_ADDR       27'b000000011001010001000000010
`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_ADDR  30'b000000011001010001000000010000
`define FIRE_DLC_ILU_CIB_CSR_B_ILU_EN_ERR_HW_ADDR       27'b000000011101010001000000010
`define FIRE_DLC_ILU_CIB_CSR_B_ILU_EN_ERR_ADDR  30'b000000011101010001000000010000

`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_WIDTH   64
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_DEPTH   1
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SLC     63:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_INT_SLC 63:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_POSITION        0
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_LOW_ADDR_WIDTH  0
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_ADDR_RANGE      26:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_READ_MASK       64'b0000000000000000000000001111000000000000000000000000000011110000
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_READ_ONLY_MASK  64'b0000000000000000000000001111000000000000000000000000000011110000
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_WRITE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SET_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_CLEAR_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_TOGGLE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_RMASK   64'b0000000000000000000000001111000000000000000000000000000011110000
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_RESERVED_BIT_MASK       64'b1111111111111111111111110000111111111111111111111111111100001111
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_POR_VALUE       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_INTERNAL_REG    0
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_EXTERNAL_DECODE_REG     1
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_ZERO_TIME_OMNI  0
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_NUM_FIELDS      8
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_S_FID    0
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_S_SLC    39:39
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_S_WIDTH  1
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_S_INT_SLC        0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_S_POSITION       39
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_S_FMASK  64'b0000000000000000000000001000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_S_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_S_POR_VALUE      1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_S_FID    1
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_S_SLC    38:38
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_S_WIDTH  1
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_S_INT_SLC        0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_S_POSITION       38
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_S_FMASK  64'b0000000000000000000000000100000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_S_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_S_POR_VALUE      1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_S_FID    2
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_S_SLC    37:37
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_S_WIDTH  1
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_S_INT_SLC        0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_S_POSITION       37
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_S_FMASK  64'b0000000000000000000000000010000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_S_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_S_POR_VALUE      1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_S_FID    3
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_S_SLC    36:36
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_S_WIDTH  1
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_S_INT_SLC        0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_S_POSITION       36
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_S_FMASK  64'b0000000000000000000000000001000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_S_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_S_POR_VALUE      1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_P_FID    4
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_P_SLC    7:7
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_P_WIDTH  1
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_P_INT_SLC        0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_P_POSITION       7
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_P_FMASK  64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_P_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_P_POR_VALUE      1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_P_FID    5
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_P_SLC    6:6
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_P_WIDTH  1
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_P_INT_SLC        0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_P_POSITION       6
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_P_FMASK  64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_P_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_P_POR_VALUE      1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_P_FID    6
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_P_SLC    5:5
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_P_WIDTH  1
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_P_INT_SLC        0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_P_POSITION       5
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_P_FMASK  64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_P_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_P_POR_VALUE      1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_P_FID    7
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_P_SLC    4:4
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_P_WIDTH  1
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_P_INT_SLC        0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_P_POSITION       4
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_P_FMASK  64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_P_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_P_POR_VALUE      1'b0

//-------------------------------------------------------
//----- Variable definitions for register dmu_ilu_cib_csr_ilu_log_err_rw1c_alias
//-------------------------------------------------------

`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_HW_ADDR   27'b000000011001010001000000011
`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_ADDR      30'b000000011001010001000000011000
`define FIRE_DLC_ILU_CIB_CSR_B_ILU_LOG_ERR_RW1C_ALIAS_HW_ADDR   27'b000000011101010001000000011
`define FIRE_DLC_ILU_CIB_CSR_B_ILU_LOG_ERR_RW1C_ALIAS_ADDR      30'b000000011101010001000000011000

`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_WIDTH       64
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_DEPTH       1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SLC 63:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_INT_SLC     63:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_POSITION    0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_LOW_ADDR_WIDTH      0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_ADDR_RANGE  26:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_READ_MASK   64'b0000000000000000000000001111000000000000000000000000000011110000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_READ_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_WRITE_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_WRITE_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SET_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_CLEAR_MASK  64'b0000000000000000000000001111000000000000000000000000000011110000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_RMASK       64'b0000000000000000000000001111000000000000000000000000000011110000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_RESERVED_BIT_MASK   64'b1111111111111111111111110000111111111111111111111111111100001111
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_HW_LD_MASK  64'b0000000000000000000000001111000000000000000000000000000011110000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_POR_VALUE   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_INTERNAL_REG        1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_ZERO_TIME_OMNI      1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_NUM_FIELDS  8
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_S_FID        0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_S_SLC        39:39
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_S_WIDTH      1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_S_INT_SLC    0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_S_POSITION   39
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_S_FMASK      64'b0000000000000000000000001000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_S_HW_LD_MASK 64'b0000000000000000000000001000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_S_POR_VALUE  1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_S_FID        1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_S_SLC        38:38
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_S_WIDTH      1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_S_INT_SLC    0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_S_POSITION   38
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_S_FMASK      64'b0000000000000000000000000100000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_S_HW_LD_MASK 64'b0000000000000000000000000100000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_S_POR_VALUE  1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_S_FID        2
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_S_SLC        37:37
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_S_WIDTH      1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_S_INT_SLC    0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_S_POSITION   37
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_S_FMASK      64'b0000000000000000000000000010000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_S_HW_LD_MASK 64'b0000000000000000000000000010000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_S_POR_VALUE  1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_S_FID        3
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_S_SLC        36:36
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_S_WIDTH      1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_S_INT_SLC    0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_S_POSITION   36
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_S_FMASK      64'b0000000000000000000000000001000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_S_HW_LD_MASK 64'b0000000000000000000000000001000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_S_POR_VALUE  1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_P_FID        4
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_P_SLC        7:7
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_P_WIDTH      1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_P_INT_SLC    0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_P_POSITION   7
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_P_FMASK      64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_P_POR_VALUE  1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_P_FID        5
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_P_SLC        6:6
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_P_WIDTH      1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_P_INT_SLC    0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_P_POSITION   6
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_P_FMASK      64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_P_POR_VALUE  1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_P_FID        6
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_P_SLC        5:5
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_P_WIDTH      1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_P_INT_SLC    0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_P_POSITION   5
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_P_FMASK      64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_P_POR_VALUE  1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_P_FID        7
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_P_SLC        4:4
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_P_WIDTH      1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_P_INT_SLC    0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_P_POSITION   4
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_P_FMASK      64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_P_POR_VALUE  1'b0

//-------------------------------------------------------
//----- Variable definitions for register dmu_ilu_cib_csr_ilu_log_err_rw1s_alias
//-------------------------------------------------------

`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_HW_ADDR   27'b000000011001010001000000100
`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_ADDR      30'b000000011001010001000000100000
`define FIRE_DLC_ILU_CIB_CSR_B_ILU_LOG_ERR_RW1S_ALIAS_HW_ADDR   27'b000000011101010001000000100
`define FIRE_DLC_ILU_CIB_CSR_B_ILU_LOG_ERR_RW1S_ALIAS_ADDR      30'b000000011101010001000000100000

`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_WIDTH       64
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_DEPTH       1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SLC 63:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_INT_SLC     63:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_POSITION    0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_LOW_ADDR_WIDTH      0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_ADDR_RANGE  26:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_READ_MASK   64'b0000000000000000000000001111000000000000000000000000000011110000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_READ_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_WRITE_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_WRITE_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SET_MASK    64'b0000000000000000000000001111000000000000000000000000000011110000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_CLEAR_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_RMASK       64'b0000000000000000000000001111000000000000000000000000000011110000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_RESERVED_BIT_MASK   64'b1111111111111111111111110000111111111111111111111111111100001111
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_HW_LD_MASK  64'b0000000000000000000000001111000000000000000000000000000011110000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_POR_VALUE   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_INTERNAL_REG        1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_ZERO_TIME_OMNI      1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_NUM_FIELDS  8
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_S_FID        0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_S_SLC        39:39
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_S_WIDTH      1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_S_INT_SLC    0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_S_POSITION   39
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_S_FMASK      64'b0000000000000000000000001000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_S_HW_LD_MASK 64'b0000000000000000000000001000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_S_POR_VALUE  1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_S_FID        1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_S_SLC        38:38
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_S_WIDTH      1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_S_INT_SLC    0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_S_POSITION   38
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_S_FMASK      64'b0000000000000000000000000100000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_S_HW_LD_MASK 64'b0000000000000000000000000100000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_S_POR_VALUE  1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_S_FID        2
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_S_SLC        37:37
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_S_WIDTH      1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_S_INT_SLC    0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_S_POSITION   37
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_S_FMASK      64'b0000000000000000000000000010000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_S_HW_LD_MASK 64'b0000000000000000000000000010000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_S_POR_VALUE  1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_S_FID        3
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_S_SLC        36:36
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_S_WIDTH      1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_S_INT_SLC    0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_S_POSITION   36
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_S_FMASK      64'b0000000000000000000000000001000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_S_HW_LD_MASK 64'b0000000000000000000000000001000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_S_POR_VALUE  1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_P_FID        4
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_P_SLC        7:7
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_P_WIDTH      1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_P_INT_SLC    0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_P_POSITION   7
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_P_FMASK      64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_P_POR_VALUE  1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_P_FID        5
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_P_SLC        6:6
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_P_WIDTH      1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_P_INT_SLC    0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_P_POSITION   6
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_P_FMASK      64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_P_POR_VALUE  1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_P_FID        6
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_P_SLC        5:5
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_P_WIDTH      1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_P_INT_SLC    0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_P_POSITION   5
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_P_FMASK      64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_P_POR_VALUE  1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_P_FID        7
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_P_SLC        4:4
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_P_WIDTH      1
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_P_INT_SLC    0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_P_POSITION   4
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_P_FMASK      64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_P_POR_VALUE  1'b0

//-------------------------------------------------------
//----- Variable definitions for register dmu_ilu_cib_csr_pec_int_en
//-------------------------------------------------------

`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_HW_ADDR       27'b000000011001010001100000000
`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_ADDR  30'b000000011001010001100000000000
`define FIRE_DLC_ILU_CIB_CSR_B_PEC_INT_EN_HW_ADDR       27'b000000011101010001100000000
`define FIRE_DLC_ILU_CIB_CSR_B_PEC_INT_EN_ADDR  30'b000000011101010001100000000000

`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_WIDTH   64
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_DEPTH   1
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_SLC     63:0
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_INT_SLC 63:0
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_POSITION        0
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_LOW_ADDR_WIDTH  0
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_ADDR_RANGE      26:0
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_READ_MASK       64'b1000000000000000000000000000000000000000000000000000000000001111
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_READ_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_WRITE_MASK      64'b1000000000000000000000000000000000000000000000000000000000001111
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_SET_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_CLEAR_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_TOGGLE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_RMASK   64'b1000000000000000000000000000000000000000000000000000000000001111
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_RESERVED_BIT_MASK       64'b0111111111111111111111111111111111111111111111111111111111110000
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_POR_VALUE       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_INTERNAL_REG    1
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_ZERO_TIME_OMNI  1
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_NUM_FIELDS      5
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_FID 0
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_SLC 63:63
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_WIDTH       1
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_INT_SLC     0:0
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_POSITION    63
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_FMASK       64'b1000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_POR_VALUE   1'b0
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_ILU_FID     1
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_ILU_SLC     3:3
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_ILU_WIDTH   1
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_ILU_INT_SLC 0:0
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_ILU_POSITION        3
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_ILU_FMASK   64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_ILU_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_ILU_POR_VALUE       1'b0
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_UE_FID      2
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_UE_SLC      2:2
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_UE_WIDTH    1
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_UE_INT_SLC  0:0
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_UE_POSITION 2
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_UE_FMASK    64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_UE_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_UE_POR_VALUE        1'b0
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_CE_FID      3
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_CE_SLC      1:1
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_CE_WIDTH    1
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_CE_INT_SLC  0:0
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_CE_POSITION 1
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_CE_FMASK    64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_CE_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_CE_POR_VALUE        1'b0
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_OE_FID      4
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_OE_SLC      0:0
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_OE_WIDTH    1
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_OE_INT_SLC  0:0
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_OE_POSITION 0
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_OE_FMASK    64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_OE_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_OE_POR_VALUE        1'b0

//-------------------------------------------------------
//----- Variable definitions for register dmu_ilu_cib_csr_pec_en_err
//-------------------------------------------------------

`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_HW_ADDR       27'b000000011001010001100000001
`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_ADDR  30'b000000011001010001100000001000
`define FIRE_DLC_ILU_CIB_CSR_B_PEC_EN_ERR_HW_ADDR       27'b000000011101010001100000001
`define FIRE_DLC_ILU_CIB_CSR_B_PEC_EN_ERR_ADDR  30'b000000011101010001100000001000

`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_WIDTH   64
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_DEPTH   1
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_SLC     63:0
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_INT_SLC 63:0
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_POSITION        0
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_LOW_ADDR_WIDTH  0
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_ADDR_RANGE      26:0
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_READ_MASK       64'b0000000000000000000000000000000000000000000000000000000000001111
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_READ_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000001111
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_WRITE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_SET_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_CLEAR_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_TOGGLE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_RMASK   64'b0000000000000000000000000000000000000000000000000000000000001111
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_RESERVED_BIT_MASK       64'b1111111111111111111111111111111111111111111111111111111111110000
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_POR_VALUE       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_INTERNAL_REG    0
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_EXTERNAL_DECODE_REG     1
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_ZERO_TIME_OMNI  0
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_NUM_FIELDS      4
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_ILU_FID 0
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_ILU_SLC 3:3
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_ILU_WIDTH       1
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_ILU_INT_SLC     0:0
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_ILU_POSITION    3
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_ILU_FMASK       64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_ILU_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_ILU_POR_VALUE   1'b0
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_UE_FID  1
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_UE_SLC  2:2
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_UE_WIDTH        1
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_UE_INT_SLC      0:0
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_UE_POSITION     2
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_UE_FMASK        64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_UE_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_UE_POR_VALUE    1'b0
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_CE_FID  2
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_CE_SLC  1:1
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_CE_WIDTH        1
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_CE_INT_SLC      0:0
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_CE_POSITION     1
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_CE_FMASK        64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_CE_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_CE_POR_VALUE    1'b0
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_OE_FID  3
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_OE_SLC  0:0
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_OE_WIDTH        1
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_OE_INT_SLC      0:0
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_OE_POSITION     0
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_OE_FMASK        64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_OE_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_OE_POR_VALUE    1'b0

//-------------------------------------------------------
//----- Variable definitions for register dmu_ilu_cib_csr_ilu_diagnos
//-------------------------------------------------------

`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_HW_ADDR      27'b000000011001010010000000000
`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ADDR 30'b000000011001010010000000000000
`define FIRE_DLC_ILU_CIB_CSR_B_ILU_DIAGNOS_HW_ADDR      27'b000000011101010010000000000
`define FIRE_DLC_ILU_CIB_CSR_B_ILU_DIAGNOS_ADDR 30'b000000011101010010000000000000

`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_WIDTH  64
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_DEPTH  1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_SLC    63:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_INT_SLC        63:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_POSITION       0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_LOW_ADDR_WIDTH 0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ADDR_RANGE     26:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_READ_MASK      64'b0000000000000000000000000000001111111111111111111111111100111100
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_WRITE_MASK     64'b0000000000000000000000000000001111111111111111111111111100001100
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_WRITE_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_SET_MASK       64'b0000000000000000000000000000000000000000000000000000000000110000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_CLEAR_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_TOGGLE_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_RMASK  64'b0000000000000000000000000000001111111111111111111111111100111100
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_RESERVED_BIT_MASK      64'b1111111111111111111111111111110000000000000000000000000011000011
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000110000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_POR_VALUE      64'b0000000000000000000000000000001111111111111111110000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_INTERNAL_REG   1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ZERO_TIME_OMNI 1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_NUM_FIELDS     23
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL1_FID     0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL1_SLC     33:33
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL1_WIDTH   1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL1_INT_SLC 0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL1_POSITION        33
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL1_FMASK   64'b0000000000000000000000000000001000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL1_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL1_POR_VALUE       1'b1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL0_FID     1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL0_SLC     32:32
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL0_WIDTH   1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL0_INT_SLC 0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL0_POSITION        32
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL0_FMASK   64'b0000000000000000000000000000000100000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL0_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL0_POR_VALUE       1'b1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX7_FID      2
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX7_SLC      31:31
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX7_WIDTH    1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX7_INT_SLC  0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX7_POSITION 31
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX7_FMASK    64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX7_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX7_POR_VALUE        1'b1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX6_FID      3
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX6_SLC      30:30
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX6_WIDTH    1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX6_INT_SLC  0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX6_POSITION 30
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX6_FMASK    64'b0000000000000000000000000000000001000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX6_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX6_POR_VALUE        1'b1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX5_FID      4
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX5_SLC      29:29
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX5_WIDTH    1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX5_INT_SLC  0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX5_POSITION 29
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX5_FMASK    64'b0000000000000000000000000000000000100000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX5_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX5_POR_VALUE        1'b1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX4_FID      5
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX4_SLC      28:28
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX4_WIDTH    1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX4_INT_SLC  0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX4_POSITION 28
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX4_FMASK    64'b0000000000000000000000000000000000010000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX4_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX4_POR_VALUE        1'b1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX3_FID      6
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX3_SLC      27:27
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX3_WIDTH    1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX3_INT_SLC  0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX3_POSITION 27
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX3_FMASK    64'b0000000000000000000000000000000000001000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX3_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX3_POR_VALUE        1'b1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX2_FID      7
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX2_SLC      26:26
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX2_WIDTH    1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX2_INT_SLC  0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX2_POSITION 26
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX2_FMASK    64'b0000000000000000000000000000000000000100000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX2_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX2_POR_VALUE        1'b1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX1_FID      8
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX1_SLC      25:25
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX1_WIDTH    1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX1_INT_SLC  0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX1_POSITION 25
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX1_FMASK    64'b0000000000000000000000000000000000000010000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX1_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX1_POR_VALUE        1'b1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX0_FID      9
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX0_SLC      24:24
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX0_WIDTH    1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX0_INT_SLC  0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX0_POSITION 24
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX0_FMASK    64'b0000000000000000000000000000000000000001000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX0_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX0_POR_VALUE        1'b1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX7_FID      10
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX7_SLC      23:23
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX7_WIDTH    1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX7_INT_SLC  0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX7_POSITION 23
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX7_FMASK    64'b0000000000000000000000000000000000000000100000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX7_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX7_POR_VALUE        1'b1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX6_FID      11
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX6_SLC      22:22
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX6_WIDTH    1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX6_INT_SLC  0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX6_POSITION 22
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX6_FMASK    64'b0000000000000000000000000000000000000000010000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX6_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX6_POR_VALUE        1'b1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX5_FID      12
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX5_SLC      21:21
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX5_WIDTH    1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX5_INT_SLC  0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX5_POSITION 21
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX5_FMASK    64'b0000000000000000000000000000000000000000001000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX5_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX5_POR_VALUE        1'b1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX4_FID      13
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX4_SLC      20:20
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX4_WIDTH    1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX4_INT_SLC  0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX4_POSITION 20
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX4_FMASK    64'b0000000000000000000000000000000000000000000100000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX4_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX4_POR_VALUE        1'b1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX3_FID      14
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX3_SLC      19:19
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX3_WIDTH    1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX3_INT_SLC  0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX3_POSITION 19
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX3_FMASK    64'b0000000000000000000000000000000000000000000010000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX3_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX3_POR_VALUE        1'b1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX2_FID      15
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX2_SLC      18:18
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX2_WIDTH    1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX2_INT_SLC  0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX2_POSITION 18
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX2_FMASK    64'b0000000000000000000000000000000000000000000001000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX2_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX2_POR_VALUE        1'b1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX1_FID      16
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX1_SLC      17:17
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX1_WIDTH    1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX1_INT_SLC  0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX1_POSITION 17
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX1_FMASK    64'b0000000000000000000000000000000000000000000000100000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX1_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX1_POR_VALUE        1'b1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX0_FID      17
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX0_SLC      16:16
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX0_WIDTH    1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX0_INT_SLC  0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX0_POSITION 16
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX0_FMASK    64'b0000000000000000000000000000000000000000000000010000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX0_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX0_POR_VALUE        1'b1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_PAR_FID    18
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_PAR_SLC    15:12
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_PAR_WIDTH  4
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_PAR_INT_SLC        3:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_PAR_POSITION       12
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_PAR_FMASK  64'b0000000000000000000000000000000000000000000000001111000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_PAR_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_PAR_POR_VALUE      4'b0000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_PAR_FID    19
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_PAR_SLC    11:8
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_PAR_WIDTH  4
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_PAR_INT_SLC        3:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_PAR_POSITION       8
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_PAR_FMASK  64'b0000000000000000000000000000000000000000000000000000111100000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_PAR_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_PAR_POR_VALUE      4'b0000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_TRIG_FID   20
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_TRIG_SLC   5:5
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_TRIG_WIDTH 1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_TRIG_INT_SLC       0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_TRIG_POSITION      5
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_TRIG_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_TRIG_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_TRIG_POR_VALUE     1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_TRIG_FID   21
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_TRIG_SLC   4:4
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_TRIG_WIDTH 1
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_TRIG_INT_SLC       0:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_TRIG_POSITION      4
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_TRIG_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_TRIG_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_TRIG_POR_VALUE     1'b0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_RATE_SCALE_FID 22
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_RATE_SCALE_SLC 3:2
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_RATE_SCALE_WIDTH       2
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_RATE_SCALE_INT_SLC     1:0
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_RATE_SCALE_POSITION    2
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_RATE_SCALE_FMASK       64'b0000000000000000000000000000000000000000000000000000000000001100
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_RATE_SCALE_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_RATE_SCALE_POR_VALUE   2'b00


`endif