// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: dmu_ilu_cib_stage_mux_only.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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// ========== Copyright Header End ============================================
module dmu_ilu_cib_stage_mux_only
ilu_log_en_select_pulse_out,
ilu_int_en_select_pulse_out,
ilu_log_err_select_pulse,
ilu_log_err_select_pulse_out,
pec_int_en_select_pulse_out,
ilu_diagnos_select_pulse,
ilu_diagnos_select_pulse_out,
ilu_log_err_rw1c_alias_out,
ilu_log_err_rw1s_alias_out,
daemon_csrbus_wr_data_in,
daemon_csrbus_wr_data_out,
//====================================================
//====================================================
input clk; // Clock signal
input [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0; // Read Data
input [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_1; // Read Data
input ilu_log_en_select_pulse; // select
output ilu_log_en_select_pulse_out; // select
input ilu_int_en_select_pulse; // select
output ilu_int_en_select_pulse_out; // select
input ilu_en_err_select; // select
output ilu_en_err_select_out; // select
input ilu_log_err_select_pulse; // select
output ilu_log_err_select_pulse_out; // select
input pec_int_en_select_pulse; // select
output pec_int_en_select_pulse_out; // select
input pec_en_err_select; // select
output pec_en_err_select_out; // select
input ilu_diagnos_select_pulse; // select
output ilu_diagnos_select_pulse_out; // select
input ilu_log_err_rw1c_alias; // SW load
output ilu_log_err_rw1c_alias_out; // alias
input ilu_log_err_rw1s_alias; // SW load
output ilu_log_err_rw1s_alias_out; // alias
input daemon_csrbus_wr_in; // csrbus_wr
output daemon_csrbus_wr_out; // csrbus_wr
input [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data
output [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // SW write
output [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data
output rst_l_out; // HW reset
output por_l_out; // HW reset
//====================================================
//====================================================
wire clk; // Clock signal
wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0; // Read Data
wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_1; // Read Data
wire ilu_log_en_select_pulse; // select
wire ilu_log_en_select_pulse_out; // select
wire ilu_int_en_select_pulse; // select
wire ilu_int_en_select_pulse_out; // select
wire ilu_en_err_select; // select
wire ilu_en_err_select_out; // select
wire ilu_log_err_select_pulse; // select
wire ilu_log_err_select_pulse_out; // select
wire pec_int_en_select_pulse; // select
wire pec_int_en_select_pulse_out; // select
wire pec_en_err_select; // select
wire pec_en_err_select_out; // select
wire ilu_diagnos_select_pulse; // select
wire ilu_diagnos_select_pulse_out; // select
wire ilu_log_err_rw1c_alias; // SW load
wire ilu_log_err_rw1c_alias_out; // alias
wire ilu_log_err_rw1s_alias; // SW load
wire ilu_log_err_rw1s_alias_out; // alias
wire daemon_csrbus_wr_in; // csrbus_wr
wire daemon_csrbus_wr_out; // csrbus_wr
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // SW write data
wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data
wire rst_l_out; // HW reset
wire por_l_out; // HW reset
//====================================================
//====================================================
assign ilu_log_en_select_pulse_out = ilu_log_en_select_pulse;
assign ilu_int_en_select_pulse_out = ilu_int_en_select_pulse;
assign ilu_en_err_select_out = ilu_en_err_select;
assign ilu_log_err_select_pulse_out = ilu_log_err_select_pulse;
assign pec_int_en_select_pulse_out = pec_int_en_select_pulse;
assign pec_en_err_select_out = pec_en_err_select;
assign ilu_diagnos_select_pulse_out = ilu_diagnos_select_pulse;
assign ilu_log_err_rw1c_alias_out = ilu_log_err_rw1c_alias;
assign ilu_log_err_rw1s_alias_out = ilu_log_err_rw1s_alias;
assign rst_l_out = rst_l;
assign por_l_out = por_l;
assign daemon_csrbus_wr_out = daemon_csrbus_wr_in;
assign daemon_csrbus_wr_data_out = daemon_csrbus_wr_data_in;
//=====================================================
//=====================================================
dmu_ilu_cib_csrpipe_5 dmu_ilu_cib_csrpipe_5_inst_1
endmodule // dmu_ilu_cib_stage_mux_only