design/sys/iop/dmu/rtl/dmu_imu_ics_defines.h

/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: dmu_imu_ics_defines.h
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
* available with the language indicating that GPLv2 or any later version
* may be used, or where a choice of which version of the GPL is applied is
* otherwise unspecified.
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
* CA 95054 USA or visit www.sun.com if you need additional information or
* have any questions.
*
*
* ========== Copyright Header End ============================================
*/
`ifdef FIRE_DLC_IMU_ICS_DEFINES
`else
`define FIRE_DLC_IMU_ICS_DEFINES

`define FIRE_DLC_IMU_ICS_INSTANCE_ID_VALUE_A 1'h0
`define FIRE_DLC_IMU_ICS_INSTANCE_ID_VALUE_B 1'h1

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_ics_csr_imu_error_log_en_reg
//-------------------------------------------------------

`define FIRE_DLC_IMU_ICS_CSR_A_IMU_ERROR_LOG_EN_REG_HW_ADDR     27'b000000011000110001000000000
`define FIRE_DLC_IMU_ICS_CSR_A_IMU_ERROR_LOG_EN_REG_ADDR        30'b000000011000110001000000000000
`define FIRE_DLC_IMU_ICS_CSR_B_IMU_ERROR_LOG_EN_REG_HW_ADDR     27'b000000011100110001000000000
`define FIRE_DLC_IMU_ICS_CSR_B_IMU_ERROR_LOG_EN_REG_ADDR        30'b000000011100110001000000000000

`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_WIDTH 64
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_DEPTH 1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SLC   63:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_INT_SLC       63:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_POSITION      0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_LOW_ADDR_WIDTH        0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_ADDR_RANGE    26:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_READ_MASK     64'b0000000000000000000000000000000000000000000000000111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_READ_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_WRITE_MASK    64'b0000000000000000000000000000000000000000000000000111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_WRITE_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SET_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_CLEAR_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_TOGGLE_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_RMASK 64'b0000000000000000000000000000000000000000000000000111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_RESERVED_BIT_MASK     64'b1111111111111111111111111111111111111111111111111000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_POR_VALUE     64'b0000000000000000000000000000000000000000000000000111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_INTERNAL_REG  1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_ZERO_TIME_OMNI        1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_NUM_FIELDS    11
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SPARE_LOG_EN_FID      0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SPARE_LOG_EN_SLC      14:10
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SPARE_LOG_EN_WIDTH    5
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SPARE_LOG_EN_INT_SLC  4:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SPARE_LOG_EN_POSITION 10
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SPARE_LOG_EN_FMASK    64'b0000000000000000000000000000000000000000000000000111110000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SPARE_LOG_EN_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SPARE_LOG_EN_POR_VALUE        5'b11111
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_OVER_LOG_EN_FID    1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_OVER_LOG_EN_SLC    9:9
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_OVER_LOG_EN_WIDTH  1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_OVER_LOG_EN_INT_SLC        0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_OVER_LOG_EN_POSITION       9
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_OVER_LOG_EN_FMASK  64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_OVER_LOG_EN_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_OVER_LOG_EN_POR_VALUE      1'b1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_NOT_EN_LOG_EN_FID  2
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_NOT_EN_LOG_EN_SLC  8:8
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_NOT_EN_LOG_EN_WIDTH        1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_NOT_EN_LOG_EN_INT_SLC      0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_NOT_EN_LOG_EN_POSITION     8
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_NOT_EN_LOG_EN_FMASK        64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_NOT_EN_LOG_EN_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_NOT_EN_LOG_EN_POR_VALUE    1'b1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_MAL_ERR_LOG_EN_FID        3
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_MAL_ERR_LOG_EN_SLC        7:7
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_MAL_ERR_LOG_EN_WIDTH      1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_MAL_ERR_LOG_EN_INT_SLC    0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_MAL_ERR_LOG_EN_POSITION   7
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_MAL_ERR_LOG_EN_FMASK      64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_MAL_ERR_LOG_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_MAL_ERR_LOG_EN_POR_VALUE  1'b1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_PAR_ERR_LOG_EN_FID        4
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_PAR_ERR_LOG_EN_SLC        6:6
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_PAR_ERR_LOG_EN_WIDTH      1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_PAR_ERR_LOG_EN_INT_SLC    0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_PAR_ERR_LOG_EN_POSITION   6
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_PAR_ERR_LOG_EN_FMASK      64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_PAR_ERR_LOG_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_PAR_ERR_LOG_EN_POR_VALUE  1'b1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMEACK_MES_NOT_EN_LOG_EN_FID  5
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMEACK_MES_NOT_EN_LOG_EN_SLC  5:5
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMEACK_MES_NOT_EN_LOG_EN_WIDTH        1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMEACK_MES_NOT_EN_LOG_EN_INT_SLC      0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMEACK_MES_NOT_EN_LOG_EN_POSITION     5
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMEACK_MES_NOT_EN_LOG_EN_FMASK        64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMEACK_MES_NOT_EN_LOG_EN_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMEACK_MES_NOT_EN_LOG_EN_POR_VALUE    1'b1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMPME_MES_NOT_EN_LOG_EN_FID   6
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMPME_MES_NOT_EN_LOG_EN_SLC   4:4
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMPME_MES_NOT_EN_LOG_EN_WIDTH 1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMPME_MES_NOT_EN_LOG_EN_INT_SLC       0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMPME_MES_NOT_EN_LOG_EN_POSITION      4
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMPME_MES_NOT_EN_LOG_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMPME_MES_NOT_EN_LOG_EN_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMPME_MES_NOT_EN_LOG_EN_POR_VALUE     1'b1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_FATAL_MES_NOT_EN_LOG_EN_FID   7
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_FATAL_MES_NOT_EN_LOG_EN_SLC   3:3
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_FATAL_MES_NOT_EN_LOG_EN_WIDTH 1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_FATAL_MES_NOT_EN_LOG_EN_INT_SLC       0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_FATAL_MES_NOT_EN_LOG_EN_POSITION      3
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_FATAL_MES_NOT_EN_LOG_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_FATAL_MES_NOT_EN_LOG_EN_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_FATAL_MES_NOT_EN_LOG_EN_POR_VALUE     1'b1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_NONFATAL_MES_NOT_EN_LOG_EN_FID        8
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_NONFATAL_MES_NOT_EN_LOG_EN_SLC        2:2
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_NONFATAL_MES_NOT_EN_LOG_EN_WIDTH      1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_NONFATAL_MES_NOT_EN_LOG_EN_INT_SLC    0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_NONFATAL_MES_NOT_EN_LOG_EN_POSITION   2
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_NONFATAL_MES_NOT_EN_LOG_EN_FMASK      64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_NONFATAL_MES_NOT_EN_LOG_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_NONFATAL_MES_NOT_EN_LOG_EN_POR_VALUE  1'b1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_COR_MES_NOT_EN_LOG_EN_FID     9
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_COR_MES_NOT_EN_LOG_EN_SLC     1:1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_COR_MES_NOT_EN_LOG_EN_WIDTH   1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_COR_MES_NOT_EN_LOG_EN_INT_SLC 0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_COR_MES_NOT_EN_LOG_EN_POSITION        1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_COR_MES_NOT_EN_LOG_EN_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_COR_MES_NOT_EN_LOG_EN_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_COR_MES_NOT_EN_LOG_EN_POR_VALUE       1'b1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_NOT_EN_LOG_EN_FID 10
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_NOT_EN_LOG_EN_SLC 0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_NOT_EN_LOG_EN_WIDTH       1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_NOT_EN_LOG_EN_INT_SLC     0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_NOT_EN_LOG_EN_POSITION    0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_NOT_EN_LOG_EN_FMASK       64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_NOT_EN_LOG_EN_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_NOT_EN_LOG_EN_POR_VALUE   1'b1

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_ics_csr_imu_int_en_reg
//-------------------------------------------------------

`define FIRE_DLC_IMU_ICS_CSR_A_IMU_INT_EN_REG_HW_ADDR   27'b000000011000110001000000001
`define FIRE_DLC_IMU_ICS_CSR_A_IMU_INT_EN_REG_ADDR      30'b000000011000110001000000001000
`define FIRE_DLC_IMU_ICS_CSR_B_IMU_INT_EN_REG_HW_ADDR   27'b000000011100110001000000001
`define FIRE_DLC_IMU_ICS_CSR_B_IMU_INT_EN_REG_ADDR      30'b000000011100110001000000001000

`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_WIDTH       64
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_DEPTH       1
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SLC 63:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_INT_SLC     63:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_POSITION    0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_LOW_ADDR_WIDTH      0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_ADDR_RANGE  26:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_READ_MASK   64'b0000000000000000011111111111111100000000000000000111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_READ_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_WRITE_MASK  64'b0000000000000000011111111111111100000000000000000111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_WRITE_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SET_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_CLEAR_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_RMASK       64'b0000000000000000011111111111111100000000000000000111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_RESERVED_BIT_MASK   64'b1111111111111111100000000000000011111111111111111000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_POR_VALUE   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_INTERNAL_REG        1
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_ZERO_TIME_OMNI      1
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NUM_FIELDS  22
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_S_INT_EN_FID  0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_S_INT_EN_SLC  46:42
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_S_INT_EN_WIDTH        5
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_S_INT_EN_INT_SLC      4:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_S_INT_EN_POSITION     42
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_S_INT_EN_FMASK        64'b0000000000000000011111000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_S_INT_EN_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_S_INT_EN_POR_VALUE    5'b00000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_S_INT_EN_FID        1
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_S_INT_EN_SLC        41:41
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_S_INT_EN_WIDTH      1
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_S_INT_EN_INT_SLC    0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_S_INT_EN_POSITION   41
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_S_INT_EN_FMASK      64'b0000000000000000000000100000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_S_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_S_INT_EN_POR_VALUE  1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_S_INT_EN_FID      2
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_S_INT_EN_SLC      40:40
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_S_INT_EN_WIDTH    1
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_S_INT_EN_INT_SLC  0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_S_INT_EN_POSITION 40
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_S_INT_EN_FMASK    64'b0000000000000000000000010000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_S_INT_EN_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_S_INT_EN_POR_VALUE        1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_S_INT_EN_FID    3
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_S_INT_EN_SLC    39:39
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_S_INT_EN_WIDTH  1
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_S_INT_EN_INT_SLC        0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_S_INT_EN_POSITION       39
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_S_INT_EN_FMASK  64'b0000000000000000000000001000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_S_INT_EN_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_S_INT_EN_POR_VALUE      1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_S_INT_EN_FID    4
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_S_INT_EN_SLC    38:38
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_S_INT_EN_WIDTH  1
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_S_INT_EN_INT_SLC        0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_S_INT_EN_POSITION       38
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_S_INT_EN_FMASK  64'b0000000000000000000000000100000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_S_INT_EN_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_S_INT_EN_POR_VALUE      1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_S_INT_EN_FID      5
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_S_INT_EN_SLC      37:37
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_S_INT_EN_WIDTH    1
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_S_INT_EN_INT_SLC  0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_S_INT_EN_POSITION 37
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_S_INT_EN_FMASK    64'b0000000000000000000000000010000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_S_INT_EN_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_S_INT_EN_POR_VALUE        1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_S_INT_EN_FID       6
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_S_INT_EN_SLC       36:36
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_S_INT_EN_WIDTH     1
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_S_INT_EN_INT_SLC   0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_S_INT_EN_POSITION  36
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_S_INT_EN_FMASK     64'b0000000000000000000000000001000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_S_INT_EN_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_S_INT_EN_POR_VALUE 1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_S_INT_EN_FID       7
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_S_INT_EN_SLC       35:35
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_S_INT_EN_WIDTH     1
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_S_INT_EN_INT_SLC   0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_S_INT_EN_POSITION  35
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_S_INT_EN_FMASK     64'b0000000000000000000000000000100000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_S_INT_EN_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_S_INT_EN_POR_VALUE 1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_S_INT_EN_FID    8
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_S_INT_EN_SLC    34:34
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_S_INT_EN_WIDTH  1
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_S_INT_EN_INT_SLC        0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_S_INT_EN_POSITION       34
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_S_INT_EN_FMASK  64'b0000000000000000000000000000010000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_S_INT_EN_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_S_INT_EN_POR_VALUE      1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_S_INT_EN_FID 9
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_S_INT_EN_SLC 33:33
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_S_INT_EN_WIDTH       1
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_S_INT_EN_INT_SLC     0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_S_INT_EN_POSITION    33
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_S_INT_EN_FMASK       64'b0000000000000000000000000000001000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_S_INT_EN_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_S_INT_EN_POR_VALUE   1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_S_INT_EN_FID     10
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_S_INT_EN_SLC     32:32
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_S_INT_EN_WIDTH   1
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_S_INT_EN_INT_SLC 0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_S_INT_EN_POSITION        32
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_S_INT_EN_FMASK   64'b0000000000000000000000000000000100000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_S_INT_EN_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_S_INT_EN_POR_VALUE       1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_P_INT_EN_FID  11
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_P_INT_EN_SLC  14:10
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_P_INT_EN_WIDTH        5
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_P_INT_EN_INT_SLC      4:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_P_INT_EN_POSITION     10
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_P_INT_EN_FMASK        64'b0000000000000000000000000000000000000000000000000111110000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_P_INT_EN_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_P_INT_EN_POR_VALUE    5'b00000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_P_INT_EN_FID        12
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_P_INT_EN_SLC        9:9
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_P_INT_EN_WIDTH      1
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_P_INT_EN_INT_SLC    0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_P_INT_EN_POSITION   9
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_P_INT_EN_FMASK      64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_P_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_P_INT_EN_POR_VALUE  1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_P_INT_EN_FID      13
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_P_INT_EN_SLC      8:8
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_P_INT_EN_WIDTH    1
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_P_INT_EN_INT_SLC  0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_P_INT_EN_POSITION 8
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_P_INT_EN_FMASK    64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_P_INT_EN_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_P_INT_EN_POR_VALUE        1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_P_INT_EN_FID    14
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_P_INT_EN_SLC    7:7
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_P_INT_EN_WIDTH  1
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_P_INT_EN_INT_SLC        0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_P_INT_EN_POSITION       7
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_P_INT_EN_FMASK  64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_P_INT_EN_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_P_INT_EN_POR_VALUE      1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_P_INT_EN_FID    15
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_P_INT_EN_SLC    6:6
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_P_INT_EN_WIDTH  1
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_P_INT_EN_INT_SLC        0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_P_INT_EN_POSITION       6
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_P_INT_EN_FMASK  64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_P_INT_EN_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_P_INT_EN_POR_VALUE      1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_P_INT_EN_FID      16
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_P_INT_EN_SLC      5:5
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_P_INT_EN_WIDTH    1
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_P_INT_EN_INT_SLC  0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_P_INT_EN_POSITION 5
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_P_INT_EN_FMASK    64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_P_INT_EN_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_P_INT_EN_POR_VALUE        1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_P_INT_EN_FID       17
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_P_INT_EN_SLC       4:4
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_P_INT_EN_WIDTH     1
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_P_INT_EN_INT_SLC   0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_P_INT_EN_POSITION  4
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_P_INT_EN_FMASK     64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_P_INT_EN_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_P_INT_EN_POR_VALUE 1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_P_INT_EN_FID       18
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_P_INT_EN_SLC       3:3
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_P_INT_EN_WIDTH     1
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_P_INT_EN_INT_SLC   0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_P_INT_EN_POSITION  3
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_P_INT_EN_FMASK     64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_P_INT_EN_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_P_INT_EN_POR_VALUE 1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_P_INT_EN_FID    19
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_P_INT_EN_SLC    2:2
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_P_INT_EN_WIDTH  1
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_P_INT_EN_INT_SLC        0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_P_INT_EN_POSITION       2
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_P_INT_EN_FMASK  64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_P_INT_EN_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_P_INT_EN_POR_VALUE      1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_P_INT_EN_FID 20
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_P_INT_EN_SLC 1:1
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_P_INT_EN_WIDTH       1
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_P_INT_EN_INT_SLC     0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_P_INT_EN_POSITION    1
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_P_INT_EN_FMASK       64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_P_INT_EN_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_P_INT_EN_POR_VALUE   1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_P_INT_EN_FID     21
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_P_INT_EN_SLC     0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_P_INT_EN_WIDTH   1
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_P_INT_EN_INT_SLC 0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_P_INT_EN_POSITION        0
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_P_INT_EN_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_P_INT_EN_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_P_INT_EN_POR_VALUE       1'b0

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_ics_csr_imu_enabled_error_status_reg
//-------------------------------------------------------

`define FIRE_DLC_IMU_ICS_CSR_A_IMU_ENABLED_ERROR_STATUS_REG_HW_ADDR     27'b000000011000110001000000010
`define FIRE_DLC_IMU_ICS_CSR_A_IMU_ENABLED_ERROR_STATUS_REG_ADDR        30'b000000011000110001000000010000
`define FIRE_DLC_IMU_ICS_CSR_B_IMU_ENABLED_ERROR_STATUS_REG_HW_ADDR     27'b000000011100110001000000010
`define FIRE_DLC_IMU_ICS_CSR_B_IMU_ENABLED_ERROR_STATUS_REG_ADDR        30'b000000011100110001000000010000

`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_WIDTH 64
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_DEPTH 1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SLC   63:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_INT_SLC       63:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_POSITION      0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_LOW_ADDR_WIDTH        0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_ADDR_RANGE    26:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_READ_MASK     64'b0000000000000000011111111111111100000000000000000111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_READ_ONLY_MASK        64'b0000000000000000011111111111111100000000000000000111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_WRITE_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_WRITE_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SET_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_CLEAR_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_TOGGLE_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_RMASK 64'b0000000000000000011111111111111100000000000000000111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_RESERVED_BIT_MASK     64'b1111111111111111100000000000000011111111111111111000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_HW_LD_MASK    64'b0000000000000000011111111111111100000000000000000111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_POR_VALUE     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_INTERNAL_REG  0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EXTERNAL_DECODE_REG   1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_ZERO_TIME_OMNI        0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NUM_FIELDS    22
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_S_FID   0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_S_SLC   46:42
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_S_WIDTH 5
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_S_INT_SLC       4:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_S_POSITION      42
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_S_FMASK 64'b0000000000000000011111000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_S_HW_LD_MASK    64'b0000000000000000011111000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_S_POR_VALUE     5'b00000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_S_FID 1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_S_SLC 41:41
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_S_WIDTH       1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_S_INT_SLC     0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_S_POSITION    41
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_S_FMASK       64'b0000000000000000000000100000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_S_HW_LD_MASK  64'b0000000000000000000000100000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_S_POR_VALUE   1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_S_FID       2
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_S_SLC       40:40
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_S_WIDTH     1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_S_INT_SLC   0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_S_POSITION  40
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_S_FMASK     64'b0000000000000000000000010000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_S_HW_LD_MASK        64'b0000000000000000000000010000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_S_POR_VALUE 1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_S_FID     3
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_S_SLC     39:39
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_S_WIDTH   1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_S_INT_SLC 0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_S_POSITION        39
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_S_FMASK   64'b0000000000000000000000001000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_S_HW_LD_MASK      64'b0000000000000000000000001000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_S_POR_VALUE       1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_S_FID     4
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_S_SLC     38:38
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_S_WIDTH   1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_S_INT_SLC 0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_S_POSITION        38
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_S_FMASK   64'b0000000000000000000000000100000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_S_HW_LD_MASK      64'b0000000000000000000000000100000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_S_POR_VALUE       1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_S_FID       5
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_S_SLC       37:37
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_S_WIDTH     1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_S_INT_SLC   0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_S_POSITION  37
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_S_FMASK     64'b0000000000000000000000000010000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_S_HW_LD_MASK        64'b0000000000000000000000000010000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_S_POR_VALUE 1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_S_FID        6
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_S_SLC        36:36
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_S_WIDTH      1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_S_INT_SLC    0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_S_POSITION   36
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_S_FMASK      64'b0000000000000000000000000001000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_S_HW_LD_MASK 64'b0000000000000000000000000001000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_S_POR_VALUE  1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_S_FID        7
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_S_SLC        35:35
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_S_WIDTH      1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_S_INT_SLC    0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_S_POSITION   35
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_S_FMASK      64'b0000000000000000000000000000100000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_S_HW_LD_MASK 64'b0000000000000000000000000000100000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_S_POR_VALUE  1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_S_FID     8
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_S_SLC     34:34
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_S_WIDTH   1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_S_INT_SLC 0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_S_POSITION        34
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_S_FMASK   64'b0000000000000000000000000000010000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_S_HW_LD_MASK      64'b0000000000000000000000000000010000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_S_POR_VALUE       1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_S_FID  9
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_S_SLC  33:33
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_S_WIDTH        1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_S_INT_SLC      0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_S_POSITION     33
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_S_FMASK        64'b0000000000000000000000000000001000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_S_HW_LD_MASK   64'b0000000000000000000000000000001000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_S_POR_VALUE    1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_S_FID      10
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_S_SLC      32:32
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_S_WIDTH    1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_S_INT_SLC  0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_S_POSITION 32
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_S_FMASK    64'b0000000000000000000000000000000100000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_S_HW_LD_MASK       64'b0000000000000000000000000000000100000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_S_POR_VALUE        1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_P_FID   11
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_P_SLC   14:10
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_P_WIDTH 5
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_P_INT_SLC       4:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_P_POSITION      10
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_P_FMASK 64'b0000000000000000000000000000000000000000000000000111110000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000111110000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_P_POR_VALUE     5'b00000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_P_FID 12
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_P_SLC 9:9
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_P_WIDTH       1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_P_INT_SLC     0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_P_POSITION    9
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_P_FMASK       64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_P_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_P_POR_VALUE   1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_P_FID       13
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_P_SLC       8:8
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_P_WIDTH     1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_P_INT_SLC   0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_P_POSITION  8
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_P_FMASK     64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_P_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_P_POR_VALUE 1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_P_FID     14
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_P_SLC     7:7
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_P_WIDTH   1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_P_INT_SLC 0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_P_POSITION        7
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_P_FMASK   64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_P_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_P_POR_VALUE       1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_P_FID     15
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_P_SLC     6:6
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_P_WIDTH   1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_P_INT_SLC 0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_P_POSITION        6
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_P_FMASK   64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_P_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_P_POR_VALUE       1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_P_FID       16
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_P_SLC       5:5
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_P_WIDTH     1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_P_INT_SLC   0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_P_POSITION  5
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_P_FMASK     64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_P_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_P_POR_VALUE 1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_P_FID        17
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_P_SLC        4:4
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_P_WIDTH      1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_P_INT_SLC    0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_P_POSITION   4
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_P_FMASK      64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_P_POR_VALUE  1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_P_FID        18
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_P_SLC        3:3
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_P_WIDTH      1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_P_INT_SLC    0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_P_POSITION   3
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_P_FMASK      64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_P_POR_VALUE  1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_P_FID     19
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_P_SLC     2:2
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_P_WIDTH   1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_P_INT_SLC 0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_P_POSITION        2
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_P_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_P_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_P_POR_VALUE       1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_P_FID  20
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_P_SLC  1:1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_P_WIDTH        1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_P_INT_SLC      0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_P_POSITION     1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_P_FMASK        64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_P_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_P_POR_VALUE    1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_P_FID      21
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_P_SLC      0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_P_WIDTH    1
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_P_INT_SLC  0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_P_POSITION 0
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_P_FMASK    64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_P_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_P_POR_VALUE        1'b0

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_ics_csr_imu_logged_error_status_reg_rw1c_alias
//-------------------------------------------------------

`define FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_HW_ADDR   27'b000000011000110001000000011
`define FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_ADDR      30'b000000011000110001000000011000
`define FIRE_DLC_IMU_ICS_CSR_B_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_HW_ADDR   27'b000000011100110001000000011
`define FIRE_DLC_IMU_ICS_CSR_B_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_ADDR      30'b000000011100110001000000011000

`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_WIDTH       64
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_DEPTH       1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SLC 63:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_INT_SLC     63:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_POSITION    0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_LOW_ADDR_WIDTH      0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_ADDR_RANGE  26:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_READ_MASK   64'b0000000000000000011111111111111100000000000000000111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_READ_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_WRITE_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_WRITE_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SET_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_CLEAR_MASK  64'b0000000000000000011111111111111100000000000000000111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_RMASK       64'b0000000000000000011111111111111100000000000000000111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_RESERVED_BIT_MASK   64'b1111111111111111100000000000000011111111111111111000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_HW_LD_MASK  64'b0000000000000000011111111111111100000000000000000111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_POR_VALUE   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_INTERNAL_REG        1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_ZERO_TIME_OMNI      1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NUM_FIELDS  22
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_FID 0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_SLC 46:42
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_WIDTH       5
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_INT_SLC     4:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_POSITION    42
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_FMASK       64'b0000000000000000011111000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_HW_LD_MASK  64'b0000000000000000011111000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_POR_VALUE   5'b00000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_S_FID       1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_S_SLC       41:41
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_S_WIDTH     1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_S_INT_SLC   0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_S_POSITION  41
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_S_FMASK     64'b0000000000000000000000100000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_S_HW_LD_MASK        64'b0000000000000000000000100000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_S_POR_VALUE 1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_S_FID     2
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_S_SLC     40:40
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_S_WIDTH   1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_S_INT_SLC 0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_S_POSITION        40
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_S_FMASK   64'b0000000000000000000000010000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_S_HW_LD_MASK      64'b0000000000000000000000010000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_S_POR_VALUE       1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_S_FID   3
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_S_SLC   39:39
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_S_WIDTH 1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_S_INT_SLC       0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_S_POSITION      39
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_S_FMASK 64'b0000000000000000000000001000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_S_HW_LD_MASK    64'b0000000000000000000000001000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_S_POR_VALUE     1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_S_FID   4
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_S_SLC   38:38
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_S_WIDTH 1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_S_INT_SLC       0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_S_POSITION      38
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_S_FMASK 64'b0000000000000000000000000100000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_S_HW_LD_MASK    64'b0000000000000000000000000100000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_S_POR_VALUE     1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_S_FID     5
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_S_SLC     37:37
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_S_WIDTH   1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_S_INT_SLC 0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_S_POSITION        37
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_S_FMASK   64'b0000000000000000000000000010000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_S_HW_LD_MASK      64'b0000000000000000000000000010000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_S_POR_VALUE       1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_S_FID      6
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_S_SLC      36:36
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_S_WIDTH    1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_S_INT_SLC  0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_S_POSITION 36
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_S_FMASK    64'b0000000000000000000000000001000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_S_HW_LD_MASK       64'b0000000000000000000000000001000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_S_POR_VALUE        1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_S_FID      7
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_S_SLC      35:35
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_S_WIDTH    1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_S_INT_SLC  0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_S_POSITION 35
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_S_FMASK    64'b0000000000000000000000000000100000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_S_HW_LD_MASK       64'b0000000000000000000000000000100000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_S_POR_VALUE        1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_S_FID   8
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_S_SLC   34:34
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_S_WIDTH 1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_S_INT_SLC       0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_S_POSITION      34
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_S_FMASK 64'b0000000000000000000000000000010000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_S_HW_LD_MASK    64'b0000000000000000000000000000010000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_S_POR_VALUE     1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_S_FID        9
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_S_SLC        33:33
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_S_WIDTH      1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_S_INT_SLC    0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_S_POSITION   33
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_S_FMASK      64'b0000000000000000000000000000001000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_S_HW_LD_MASK 64'b0000000000000000000000000000001000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_S_POR_VALUE  1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_S_FID    10
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_S_SLC    32:32
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_S_WIDTH  1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_S_INT_SLC        0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_S_POSITION       32
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_S_FMASK  64'b0000000000000000000000000000000100000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_S_HW_LD_MASK     64'b0000000000000000000000000000000100000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_S_POR_VALUE      1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_FID 11
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_SLC 14:10
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_WIDTH       5
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_INT_SLC     4:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_POSITION    10
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_FMASK       64'b0000000000000000000000000000000000000000000000000111110000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000111110000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_POR_VALUE   5'b00000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_P_FID       12
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_P_SLC       9:9
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_P_WIDTH     1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_P_INT_SLC   0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_P_POSITION  9
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_P_FMASK     64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_P_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_P_POR_VALUE 1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_P_FID     13
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_P_SLC     8:8
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_P_WIDTH   1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_P_INT_SLC 0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_P_POSITION        8
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_P_FMASK   64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_P_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_P_POR_VALUE       1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_P_FID   14
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_P_SLC   7:7
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_P_WIDTH 1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_P_INT_SLC       0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_P_POSITION      7
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_P_POR_VALUE     1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_P_FID   15
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_P_SLC   6:6
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_P_WIDTH 1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_P_INT_SLC       0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_P_POSITION      6
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_P_POR_VALUE     1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_P_FID     16
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_P_SLC     5:5
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_P_WIDTH   1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_P_INT_SLC 0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_P_POSITION        5
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_P_FMASK   64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_P_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_P_POR_VALUE       1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_P_FID      17
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_P_SLC      4:4
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_P_WIDTH    1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_P_INT_SLC  0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_P_POSITION 4
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_P_FMASK    64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_P_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_P_POR_VALUE        1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_P_FID      18
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_P_SLC      3:3
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_P_WIDTH    1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_P_INT_SLC  0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_P_POSITION 3
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_P_FMASK    64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_P_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_P_POR_VALUE        1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_P_FID   19
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_P_SLC   2:2
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_P_WIDTH 1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_P_INT_SLC       0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_P_POSITION      2
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_P_POR_VALUE     1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_P_FID        20
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_P_SLC        1:1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_P_WIDTH      1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_P_INT_SLC    0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_P_POSITION   1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_P_FMASK      64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_P_POR_VALUE  1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_P_FID    21
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_P_SLC    0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_P_WIDTH  1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_P_INT_SLC        0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_P_POSITION       0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_P_FMASK  64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_P_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_P_POR_VALUE      1'b0

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_ics_csr_imu_logged_error_status_reg_rw1s_alias
//-------------------------------------------------------

`define FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_HW_ADDR   27'b000000011000110001000000100
`define FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_ADDR      30'b000000011000110001000000100000
`define FIRE_DLC_IMU_ICS_CSR_B_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_HW_ADDR   27'b000000011100110001000000100
`define FIRE_DLC_IMU_ICS_CSR_B_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_ADDR      30'b000000011100110001000000100000

`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_WIDTH       64
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_DEPTH       1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SLC 63:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_INT_SLC     63:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_POSITION    0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_LOW_ADDR_WIDTH      0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_ADDR_RANGE  26:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_READ_MASK   64'b0000000000000000011111111111111100000000000000000111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_READ_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_WRITE_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_WRITE_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SET_MASK    64'b0000000000000000011111111111111100000000000000000111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_CLEAR_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_RMASK       64'b0000000000000000011111111111111100000000000000000111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_RESERVED_BIT_MASK   64'b1111111111111111100000000000000011111111111111111000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_HW_LD_MASK  64'b0000000000000000011111111111111100000000000000000111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_POR_VALUE   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_INTERNAL_REG        1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_ZERO_TIME_OMNI      1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NUM_FIELDS  22
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_S_FID 0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_S_SLC 46:42
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_S_WIDTH       5
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_S_INT_SLC     4:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_S_POSITION    42
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_S_FMASK       64'b0000000000000000011111000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_S_HW_LD_MASK  64'b0000000000000000011111000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_S_POR_VALUE   5'b00000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_S_FID       1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_S_SLC       41:41
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_S_WIDTH     1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_S_INT_SLC   0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_S_POSITION  41
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_S_FMASK     64'b0000000000000000000000100000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_S_HW_LD_MASK        64'b0000000000000000000000100000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_S_POR_VALUE 1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_S_FID     2
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_S_SLC     40:40
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_S_WIDTH   1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_S_INT_SLC 0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_S_POSITION        40
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_S_FMASK   64'b0000000000000000000000010000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_S_HW_LD_MASK      64'b0000000000000000000000010000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_S_POR_VALUE       1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_S_FID   3
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_S_SLC   39:39
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_S_WIDTH 1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_S_INT_SLC       0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_S_POSITION      39
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_S_FMASK 64'b0000000000000000000000001000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_S_HW_LD_MASK    64'b0000000000000000000000001000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_S_POR_VALUE     1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_S_FID   4
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_S_SLC   38:38
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_S_WIDTH 1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_S_INT_SLC       0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_S_POSITION      38
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_S_FMASK 64'b0000000000000000000000000100000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_S_HW_LD_MASK    64'b0000000000000000000000000100000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_S_POR_VALUE     1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_S_FID     5
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_S_SLC     37:37
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_S_WIDTH   1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_S_INT_SLC 0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_S_POSITION        37
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_S_FMASK   64'b0000000000000000000000000010000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_S_HW_LD_MASK      64'b0000000000000000000000000010000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_S_POR_VALUE       1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_S_FID      6
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_S_SLC      36:36
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_S_WIDTH    1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_S_INT_SLC  0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_S_POSITION 36
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_S_FMASK    64'b0000000000000000000000000001000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_S_HW_LD_MASK       64'b0000000000000000000000000001000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_S_POR_VALUE        1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_S_FID      7
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_S_SLC      35:35
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_S_WIDTH    1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_S_INT_SLC  0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_S_POSITION 35
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_S_FMASK    64'b0000000000000000000000000000100000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_S_HW_LD_MASK       64'b0000000000000000000000000000100000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_S_POR_VALUE        1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_S_FID   8
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_S_SLC   34:34
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_S_WIDTH 1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_S_INT_SLC       0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_S_POSITION      34
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_S_FMASK 64'b0000000000000000000000000000010000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_S_HW_LD_MASK    64'b0000000000000000000000000000010000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_S_POR_VALUE     1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_S_FID        9
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_S_SLC        33:33
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_S_WIDTH      1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_S_INT_SLC    0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_S_POSITION   33
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_S_FMASK      64'b0000000000000000000000000000001000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_S_HW_LD_MASK 64'b0000000000000000000000000000001000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_S_POR_VALUE  1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_S_FID    10
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_S_SLC    32:32
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_S_WIDTH  1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_S_INT_SLC        0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_S_POSITION       32
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_S_FMASK  64'b0000000000000000000000000000000100000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_S_HW_LD_MASK     64'b0000000000000000000000000000000100000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_S_POR_VALUE      1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_P_FID 11
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_P_SLC 14:10
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_P_WIDTH       5
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_P_INT_SLC     4:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_P_POSITION    10
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_P_FMASK       64'b0000000000000000000000000000000000000000000000000111110000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_P_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000111110000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_P_POR_VALUE   5'b00000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_P_FID       12
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_P_SLC       9:9
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_P_WIDTH     1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_P_INT_SLC   0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_P_POSITION  9
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_P_FMASK     64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_P_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_P_POR_VALUE 1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_P_FID     13
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_P_SLC     8:8
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_P_WIDTH   1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_P_INT_SLC 0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_P_POSITION        8
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_P_FMASK   64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_P_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_P_POR_VALUE       1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_P_FID   14
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_P_SLC   7:7
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_P_WIDTH 1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_P_INT_SLC       0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_P_POSITION      7
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_P_POR_VALUE     1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_P_FID   15
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_P_SLC   6:6
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_P_WIDTH 1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_P_INT_SLC       0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_P_POSITION      6
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_P_POR_VALUE     1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_P_FID     16
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_P_SLC     5:5
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_P_WIDTH   1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_P_INT_SLC 0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_P_POSITION        5
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_P_FMASK   64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_P_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_P_POR_VALUE       1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_P_FID      17
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_P_SLC      4:4
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_P_WIDTH    1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_P_INT_SLC  0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_P_POSITION 4
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_P_FMASK    64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_P_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_P_POR_VALUE        1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_P_FID      18
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_P_SLC      3:3
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_P_WIDTH    1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_P_INT_SLC  0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_P_POSITION 3
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_P_FMASK    64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_P_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_P_POR_VALUE        1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_P_FID   19
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_P_SLC   2:2
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_P_WIDTH 1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_P_INT_SLC       0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_P_POSITION      2
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_P_POR_VALUE     1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_P_FID        20
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_P_SLC        1:1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_P_WIDTH      1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_P_INT_SLC    0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_P_POSITION   1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_P_FMASK      64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_P_POR_VALUE  1'b0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_P_FID    21
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_P_SLC    0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_P_WIDTH  1
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_P_INT_SLC        0:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_P_POSITION       0
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_P_FMASK  64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_P_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_P_POR_VALUE      1'b0

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_ics_csr_imu_rds_error_log_reg
//-------------------------------------------------------

`define FIRE_DLC_IMU_ICS_CSR_A_IMU_RDS_ERROR_LOG_REG_HW_ADDR    27'b000000011000110001000000101
`define FIRE_DLC_IMU_ICS_CSR_A_IMU_RDS_ERROR_LOG_REG_ADDR       30'b000000011000110001000000101000
`define FIRE_DLC_IMU_ICS_CSR_B_IMU_RDS_ERROR_LOG_REG_HW_ADDR    27'b000000011100110001000000101
`define FIRE_DLC_IMU_ICS_CSR_B_IMU_RDS_ERROR_LOG_REG_ADDR       30'b000000011100110001000000101000

`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_WIDTH        64
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_DEPTH        1
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_SLC  63:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_INT_SLC      63:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_POSITION     0
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_LOW_ADDR_WIDTH       0
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_ADDR_RANGE   26:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_READ_MASK    64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_READ_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_WRITE_MASK   64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_WRITE_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_SET_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_CLEAR_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TOGGLE_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_RMASK        64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_RESERVED_BIT_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_HW_LD_MASK   64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_POR_VALUE    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_INTERNAL_REG 1
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_ZERO_TIME_OMNI       1
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_NUM_FIELDS   6
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TYPE_FID     0
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TYPE_SLC     63:58
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TYPE_WIDTH   6
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TYPE_INT_SLC 5:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TYPE_POSITION        58
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TYPE_FMASK   64'b1111110000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TYPE_HW_LD_MASK      64'b1111110000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TYPE_POR_VALUE       6'b000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_LENGTH_FID   1
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_LENGTH_SLC   57:48
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_LENGTH_WIDTH 10
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_LENGTH_INT_SLC       9:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_LENGTH_POSITION      48
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_LENGTH_FMASK 64'b0000001111111111000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_LENGTH_HW_LD_MASK    64'b0000001111111111000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_LENGTH_POR_VALUE     10'b0000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_REQ_ID_FID   2
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_REQ_ID_SLC   47:32
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_REQ_ID_WIDTH 16
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_REQ_ID_INT_SLC       15:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_REQ_ID_POSITION      32
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_REQ_ID_FMASK 64'b0000000000000000111111111111111100000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_REQ_ID_HW_LD_MASK    64'b0000000000000000111111111111111100000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_REQ_ID_POR_VALUE     16'b0000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TLP_TAG_FID  3
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TLP_TAG_SLC  31:24
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TLP_TAG_WIDTH        8
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TLP_TAG_INT_SLC      7:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TLP_TAG_POSITION     24
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TLP_TAG_FMASK        64'b0000000000000000000000000000000011111111000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TLP_TAG_HW_LD_MASK   64'b0000000000000000000000000000000011111111000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TLP_TAG_POR_VALUE    8'b00000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_BE_MESS_CODE_FID     4
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_BE_MESS_CODE_SLC     23:16
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_BE_MESS_CODE_WIDTH   8
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_BE_MESS_CODE_INT_SLC 7:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_BE_MESS_CODE_POSITION        16
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_BE_MESS_CODE_FMASK   64'b0000000000000000000000000000000000000000111111110000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_BE_MESS_CODE_HW_LD_MASK      64'b0000000000000000000000000000000000000000111111110000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_BE_MESS_CODE_POR_VALUE       8'b00000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_MSI_DATA_FID 5
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_MSI_DATA_SLC 15:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_MSI_DATA_WIDTH       16
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_MSI_DATA_INT_SLC     15:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_MSI_DATA_POSITION    0
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_MSI_DATA_FMASK       64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_MSI_DATA_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_MSI_DATA_POR_VALUE   16'b0000000000000000

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_ics_csr_imu_scs_error_log_reg
//-------------------------------------------------------

`define FIRE_DLC_IMU_ICS_CSR_A_IMU_SCS_ERROR_LOG_REG_HW_ADDR    27'b000000011000110001000000110
`define FIRE_DLC_IMU_ICS_CSR_A_IMU_SCS_ERROR_LOG_REG_ADDR       30'b000000011000110001000000110000
`define FIRE_DLC_IMU_ICS_CSR_B_IMU_SCS_ERROR_LOG_REG_HW_ADDR    27'b000000011100110001000000110
`define FIRE_DLC_IMU_ICS_CSR_B_IMU_SCS_ERROR_LOG_REG_ADDR       30'b000000011100110001000000110000

`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_WIDTH        64
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_DEPTH        1
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_SLC  63:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_INT_SLC      63:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_POSITION     0
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_LOW_ADDR_WIDTH       0
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_ADDR_RANGE   26:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_READ_MASK    64'b1111111111111111111111111111111111111111111111110000000000111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_READ_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_WRITE_MASK   64'b1111111111111111111111111111111111111111111111110000000000111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_WRITE_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_SET_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_CLEAR_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TOGGLE_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_RMASK        64'b1111111111111111111111111111111111111111111111110000000000111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_RESERVED_BIT_MASK    64'b0000000000000000000000000000000000000000000000001111111111000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_HW_LD_MASK   64'b1111111111111111111111111111111111111111111111110000000000111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_POR_VALUE    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_INTERNAL_REG 1
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_ZERO_TIME_OMNI       1
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_NUM_FIELDS   6
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TYPE_FID     0
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TYPE_SLC     63:58
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TYPE_WIDTH   6
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TYPE_INT_SLC 5:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TYPE_POSITION        58
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TYPE_FMASK   64'b1111110000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TYPE_HW_LD_MASK      64'b1111110000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TYPE_POR_VALUE       6'b000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_LENGTH_FID   1
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_LENGTH_SLC   57:48
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_LENGTH_WIDTH 10
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_LENGTH_INT_SLC       9:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_LENGTH_POSITION      48
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_LENGTH_FMASK 64'b0000001111111111000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_LENGTH_HW_LD_MASK    64'b0000001111111111000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_LENGTH_POR_VALUE     10'b0000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_REQ_ID_FID   2
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_REQ_ID_SLC   47:32
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_REQ_ID_WIDTH 16
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_REQ_ID_INT_SLC       15:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_REQ_ID_POSITION      32
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_REQ_ID_FMASK 64'b0000000000000000111111111111111100000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_REQ_ID_HW_LD_MASK    64'b0000000000000000111111111111111100000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_REQ_ID_POR_VALUE     16'b0000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TLP_TAG_FID  3
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TLP_TAG_SLC  31:24
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TLP_TAG_WIDTH        8
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TLP_TAG_INT_SLC      7:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TLP_TAG_POSITION     24
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TLP_TAG_FMASK        64'b0000000000000000000000000000000011111111000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TLP_TAG_HW_LD_MASK   64'b0000000000000000000000000000000011111111000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TLP_TAG_POR_VALUE    8'b00000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_BE_MESS_CODE_FID     4
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_BE_MESS_CODE_SLC     23:16
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_BE_MESS_CODE_WIDTH   8
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_BE_MESS_CODE_INT_SLC 7:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_BE_MESS_CODE_POSITION        16
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_BE_MESS_CODE_FMASK   64'b0000000000000000000000000000000000000000111111110000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_BE_MESS_CODE_HW_LD_MASK      64'b0000000000000000000000000000000000000000111111110000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_BE_MESS_CODE_POR_VALUE       8'b00000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_EQ_NUM_FID   5
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_EQ_NUM_SLC   5:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_EQ_NUM_WIDTH 6
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_EQ_NUM_INT_SLC       5:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_EQ_NUM_POSITION      0
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_EQ_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000000000111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_EQ_NUM_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_EQ_NUM_POR_VALUE     6'b000000

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_ics_csr_imu_eqs_error_log_reg
//-------------------------------------------------------

`define FIRE_DLC_IMU_ICS_CSR_A_IMU_EQS_ERROR_LOG_REG_HW_ADDR    27'b000000011000110001000000111
`define FIRE_DLC_IMU_ICS_CSR_A_IMU_EQS_ERROR_LOG_REG_ADDR       30'b000000011000110001000000111000
`define FIRE_DLC_IMU_ICS_CSR_B_IMU_EQS_ERROR_LOG_REG_HW_ADDR    27'b000000011100110001000000111
`define FIRE_DLC_IMU_ICS_CSR_B_IMU_EQS_ERROR_LOG_REG_ADDR       30'b000000011100110001000000111000

`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_WIDTH        64
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_DEPTH        1
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_SLC  63:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_INT_SLC      63:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_POSITION     0
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_LOW_ADDR_WIDTH       0
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_ADDR_RANGE   26:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_READ_MASK    64'b0000000000000000000000000000000000000000000000000000000000111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_READ_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_WRITE_MASK   64'b0000000000000000000000000000000000000000000000000000000000111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_WRITE_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_SET_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_CLEAR_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_TOGGLE_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_RMASK        64'b0000000000000000000000000000000000000000000000000000000000111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_RESERVED_BIT_MASK    64'b1111111111111111111111111111111111111111111111111111111111000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_POR_VALUE    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_INTERNAL_REG 1
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_ZERO_TIME_OMNI       1
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_NUM_FIELDS   1
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_EQ_NUM_FID   0
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_EQ_NUM_SLC   5:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_EQ_NUM_WIDTH 6
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_EQ_NUM_INT_SLC       5:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_EQ_NUM_POSITION      0
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_EQ_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000000000111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_EQ_NUM_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_EQ_NUM_POR_VALUE     6'b000000

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_ics_csr_dmc_interrupt_mask_reg
//-------------------------------------------------------

`define FIRE_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_MASK_REG_HW_ADDR   27'b000000011000110001100000000
`define FIRE_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_MASK_REG_ADDR      30'b000000011000110001100000000000
`define FIRE_DLC_IMU_ICS_CSR_B_DMC_INTERRUPT_MASK_REG_HW_ADDR   27'b000000011100110001100000000
`define FIRE_DLC_IMU_ICS_CSR_B_DMC_INTERRUPT_MASK_REG_ADDR      30'b000000011100110001100000000000

`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_WIDTH       64
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DEPTH       1
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_SLC 63:0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_INT_SLC     63:0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_POSITION    0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_LOW_ADDR_WIDTH      0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_ADDR_RANGE  26:0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_READ_MASK   64'b1100000000000000000000000000000000000000000000000000000000000011
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_READ_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_WRITE_MASK  64'b1100000000000000000000000000000000000000000000000000000000000011
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_WRITE_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_SET_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_CLEAR_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_RMASK       64'b1100000000000000000000000000000000000000000000000000000000000011
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_RESERVED_BIT_MASK   64'b0011111111111111111111111111111111111111111111111111111111111100
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_POR_VALUE   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_INTERNAL_REG        1
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_ZERO_TIME_OMNI      1
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_NUM_FIELDS  4
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DMC_FID     0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DMC_SLC     63:63
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DMC_WIDTH   1
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DMC_INT_SLC 0:0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DMC_POSITION        63
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DMC_FMASK   64'b1000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DMC_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DMC_POR_VALUE       1'b0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DEBUG_TRIG_EN_FID   1
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DEBUG_TRIG_EN_SLC   62:62
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DEBUG_TRIG_EN_WIDTH 1
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DEBUG_TRIG_EN_INT_SLC       0:0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DEBUG_TRIG_EN_POSITION      62
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DEBUG_TRIG_EN_FMASK 64'b0100000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DEBUG_TRIG_EN_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DEBUG_TRIG_EN_POR_VALUE     1'b0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_MMU_FID     2
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_MMU_SLC     1:1
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_MMU_WIDTH   1
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_MMU_INT_SLC 0:0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_MMU_POSITION        1
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_MMU_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_MMU_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_MMU_POR_VALUE       1'b0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_IMU_FID     3
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_IMU_SLC     0:0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_IMU_WIDTH   1
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_IMU_INT_SLC 0:0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_IMU_POSITION        0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_IMU_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_IMU_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_IMU_POR_VALUE       1'b0

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_ics_csr_dmc_interrupt_status_reg
//-------------------------------------------------------

`define FIRE_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_STATUS_REG_HW_ADDR 27'b000000011000110001100000001
`define FIRE_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_STATUS_REG_ADDR    30'b000000011000110001100000001000
`define FIRE_DLC_IMU_ICS_CSR_B_DMC_INTERRUPT_STATUS_REG_HW_ADDR 27'b000000011100110001100000001
`define FIRE_DLC_IMU_ICS_CSR_B_DMC_INTERRUPT_STATUS_REG_ADDR    30'b000000011100110001100000001000

`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_WIDTH     64
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_DEPTH     1
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_SLC       63:0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_INT_SLC   63:0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_POSITION  0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_LOW_ADDR_WIDTH    0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_ADDR_RANGE        26:0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_READ_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000011
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_WRITE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_WRITE_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_SET_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_CLEAR_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_TOGGLE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_RMASK     64'b0000000000000000000000000000000000000000000000000000000000000011
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_INTERNAL_REG      0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_EXTERNAL_DECODE_REG       1
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_ZERO_TIME_OMNI    0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_NUM_FIELDS        2
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_MMU_FID   0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_MMU_SLC   1:1
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_MMU_WIDTH 1
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_MMU_INT_SLC       0:0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_MMU_POSITION      1
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_MMU_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_MMU_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_MMU_POR_VALUE     1'b0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_IMU_FID   1
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_IMU_SLC   0:0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_IMU_WIDTH 1
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_IMU_INT_SLC       0:0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_IMU_POSITION      0
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_IMU_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_IMU_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_IMU_POR_VALUE     1'b0

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_ics_csr_imu_perf_cntrl
//-------------------------------------------------------

`define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNTRL_HW_ADDR   27'b000000011000110010000000000
`define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNTRL_ADDR      30'b000000011000110010000000000000
`define FIRE_DLC_IMU_ICS_CSR_B_IMU_PERF_CNTRL_HW_ADDR   27'b000000011100110010000000000
`define FIRE_DLC_IMU_ICS_CSR_B_IMU_PERF_CNTRL_ADDR      30'b000000011100110010000000000000

`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_WIDTH       64
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_DEPTH       1
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SLC 63:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_INT_SLC     63:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_POSITION    0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_LOW_ADDR_WIDTH      0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_ADDR_RANGE  26:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_READ_MASK   64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_READ_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_WRITE_MASK  64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_WRITE_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SET_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_CLEAR_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_RMASK       64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_RESERVED_BIT_MASK   64'b1111111111111111111111111111111111111111111111110000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_POR_VALUE   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_INTERNAL_REG        1
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_ZERO_TIME_OMNI      1
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_NUM_FIELDS  2
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL1_FID    0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL1_SLC    15:8
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL1_WIDTH  8
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL1_INT_SLC        7:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL1_POSITION       8
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL1_FMASK  64'b0000000000000000000000000000000000000000000000001111111100000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL1_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL1_POR_VALUE      8'b00000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL0_FID    1
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL0_SLC    7:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL0_WIDTH  8
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL0_INT_SLC        7:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL0_POSITION       0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL0_FMASK  64'b0000000000000000000000000000000000000000000000000000000011111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL0_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL0_POR_VALUE      8'b00000000

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_ics_csr_imu_perf_cnt0
//-------------------------------------------------------

`define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT0_HW_ADDR    27'b000000011000110010000000001
`define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT0_ADDR       30'b000000011000110010000000001000
`define FIRE_DLC_IMU_ICS_CSR_B_IMU_PERF_CNT0_HW_ADDR    27'b000000011100110010000000001
`define FIRE_DLC_IMU_ICS_CSR_B_IMU_PERF_CNT0_ADDR       30'b000000011100110010000000001000

`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_WIDTH        64
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_DEPTH        1
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_SLC  63:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_INT_SLC      63:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_POSITION     0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_LOW_ADDR_WIDTH       0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_ADDR_RANGE   26:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_READ_MASK    64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_READ_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_WRITE_MASK   64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_WRITE_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_SET_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_CLEAR_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_TOGGLE_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_RMASK        64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_RESERVED_BIT_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_HW_LD_MASK   64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_POR_VALUE    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_INTERNAL_REG 1
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_ZERO_TIME_OMNI       1
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_NUM_FIELDS   1
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_CNT_FID      0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_CNT_SLC      63:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_CNT_WIDTH    64
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_CNT_INT_SLC  63:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_CNT_POSITION 0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_CNT_FMASK    64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_CNT_HW_LD_MASK       64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_CNT_POR_VALUE        64'b0000000000000000000000000000000000000000000000000000000000000000

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_ics_csr_imu_perf_cnt1
//-------------------------------------------------------

`define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT1_HW_ADDR    27'b000000011000110010000000010
`define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT1_ADDR       30'b000000011000110010000000010000
`define FIRE_DLC_IMU_ICS_CSR_B_IMU_PERF_CNT1_HW_ADDR    27'b000000011100110010000000010
`define FIRE_DLC_IMU_ICS_CSR_B_IMU_PERF_CNT1_ADDR       30'b000000011100110010000000010000

`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_WIDTH        64
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_DEPTH        1
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_SLC  63:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_INT_SLC      63:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_POSITION     0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_LOW_ADDR_WIDTH       0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_ADDR_RANGE   26:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_READ_MASK    64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_READ_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_WRITE_MASK   64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_WRITE_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_SET_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_CLEAR_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_TOGGLE_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_RMASK        64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_RESERVED_BIT_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_HW_LD_MASK   64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_POR_VALUE    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_INTERNAL_REG 1
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_ZERO_TIME_OMNI       1
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_NUM_FIELDS   1
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_CNT_FID      0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_CNT_SLC      63:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_CNT_WIDTH    64
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_CNT_INT_SLC  63:0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_CNT_POSITION 0
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_CNT_FMASK    64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_CNT_HW_LD_MASK       64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_CNT_POR_VALUE        64'b0000000000000000000000000000000000000000000000000000000000000000

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_ics_csr_msi_32_addr_reg
//-------------------------------------------------------

`define FIRE_DLC_IMU_ICS_CSR_A_MSI_32_ADDR_REG_HW_ADDR  27'b000000011000110100000000000
`define FIRE_DLC_IMU_ICS_CSR_A_MSI_32_ADDR_REG_ADDR     30'b000000011000110100000000000000
`define FIRE_DLC_IMU_ICS_CSR_B_MSI_32_ADDR_REG_HW_ADDR  27'b000000011100110100000000000
`define FIRE_DLC_IMU_ICS_CSR_B_MSI_32_ADDR_REG_ADDR     30'b000000011100110100000000000000

`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_WIDTH      64
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_DEPTH      1
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_SLC        63:0
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_INT_SLC    63:0
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_POSITION   0
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_LOW_ADDR_WIDTH     0
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_ADDR_RANGE 26:0
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_READ_MASK  64'b0000000000000000000000000000000011111111111111110000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_READ_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_WRITE_MASK 64'b0000000000000000000000000000000011111111111111110000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_WRITE_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_SET_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_TOGGLE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_RMASK      64'b0000000000000000000000000000000011111111111111110000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_RESERVED_BIT_MASK  64'b1111111111111111111111111111111100000000000000001111111111111111
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_POR_VALUE  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_INTERNAL_REG       1
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_ZERO_TIME_OMNI     1
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_NUM_FIELDS 1
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_ADDR_FID   0
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_ADDR_SLC   31:16
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_ADDR_WIDTH 16
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_ADDR_INT_SLC       15:0
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_ADDR_POSITION      16
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_ADDR_FMASK 64'b0000000000000000000000000000000011111111111111110000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_ADDR_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_ADDR_POR_VALUE     16'b0000000000000000

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_ics_csr_msi_64_addr_reg
//-------------------------------------------------------

`define FIRE_DLC_IMU_ICS_CSR_A_MSI_64_ADDR_REG_HW_ADDR  27'b000000011000110100000000001
`define FIRE_DLC_IMU_ICS_CSR_A_MSI_64_ADDR_REG_ADDR     30'b000000011000110100000000001000
`define FIRE_DLC_IMU_ICS_CSR_B_MSI_64_ADDR_REG_HW_ADDR  27'b000000011100110100000000001
`define FIRE_DLC_IMU_ICS_CSR_B_MSI_64_ADDR_REG_ADDR     30'b000000011100110100000000001000

`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_WIDTH      64
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_DEPTH      1
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_SLC        63:0
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_INT_SLC    63:0
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_POSITION   0
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_LOW_ADDR_WIDTH     0
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_ADDR_RANGE 26:0
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_READ_MASK  64'b1111111111111111111111111111111111111111111111110000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_READ_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_WRITE_MASK 64'b1111111111111111111111111111111111111111111111110000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_WRITE_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_SET_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_TOGGLE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_RMASK      64'b1111111111111111111111111111111111111111111111110000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_RESERVED_BIT_MASK  64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_POR_VALUE  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_INTERNAL_REG       1
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_ZERO_TIME_OMNI     1
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_NUM_FIELDS 1
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_ADDR_FID   0
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_ADDR_SLC   63:16
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_ADDR_WIDTH 48
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_ADDR_INT_SLC       47:0
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_ADDR_POSITION      16
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_ADDR_FMASK 64'b1111111111111111111111111111111111111111111111110000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_ADDR_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_ADDR_POR_VALUE     48'b000000000000000000000000000000000000000000000000

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_ics_csr_mem_64_pcie_offset_reg
//-------------------------------------------------------

`define FIRE_DLC_IMU_ICS_CSR_A_MEM_64_PCIE_OFFSET_REG_HW_ADDR   27'b000000011000110100000000011
`define FIRE_DLC_IMU_ICS_CSR_A_MEM_64_PCIE_OFFSET_REG_ADDR      30'b000000011000110100000000011000
`define FIRE_DLC_IMU_ICS_CSR_B_MEM_64_PCIE_OFFSET_REG_HW_ADDR   27'b000000011100110100000000011
`define FIRE_DLC_IMU_ICS_CSR_B_MEM_64_PCIE_OFFSET_REG_ADDR      30'b000000011100110100000000011000

`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_WIDTH       64
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_DEPTH       1
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SLC 63:0
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_INT_SLC     63:0
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_POSITION    0
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_LOW_ADDR_WIDTH      0
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_ADDR_RANGE  26:0
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_READ_MASK   64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_READ_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_WRITE_MASK  64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_WRITE_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SET_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_CLEAR_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_RMASK       64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_RESERVED_BIT_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_HW_LD_MASK  64'b0000000000000000000000000000000000000000111111111111111100000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_POR_VALUE   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_INTERNAL_REG        1
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_ZERO_TIME_OMNI      1
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_NUM_FIELDS  11
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_ADDR_FID    0
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_ADDR_SLC    63:24
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_ADDR_WIDTH  40
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_ADDR_INT_SLC        39:0
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_ADDR_POSITION       24
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_ADDR_FMASK  64'b1111111111111111111111111111111111111111000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_ADDR_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_ADDR_POR_VALUE      40'b0000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_7_FID    1
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_7_SLC    23:23
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_7_WIDTH  1
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_7_INT_SLC        0:0
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_7_POSITION       23
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_7_FMASK  64'b0000000000000000000000000000000000000000100000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_7_HW_LD_MASK     64'b0000000000000000000000000000000000000000100000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_7_POR_VALUE      1'b0
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_6_FID    2
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_6_SLC    22:22
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_6_WIDTH  1
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_6_INT_SLC        0:0
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_6_POSITION       22
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_6_FMASK  64'b0000000000000000000000000000000000000000010000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_6_HW_LD_MASK     64'b0000000000000000000000000000000000000000010000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_6_POR_VALUE      1'b0
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_5_FID    3
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_5_SLC    21:21
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_5_WIDTH  1
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_5_INT_SLC        0:0
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_5_POSITION       21
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_5_FMASK  64'b0000000000000000000000000000000000000000001000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_5_HW_LD_MASK     64'b0000000000000000000000000000000000000000001000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_5_POR_VALUE      1'b0
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_4_FID    4
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_4_SLC    20:20
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_4_WIDTH  1
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_4_INT_SLC        0:0
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_4_POSITION       20
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_4_FMASK  64'b0000000000000000000000000000000000000000000100000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_4_HW_LD_MASK     64'b0000000000000000000000000000000000000000000100000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_4_POR_VALUE      1'b0
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_3_FID    5
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_3_SLC    19:19
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_3_WIDTH  1
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_3_INT_SLC        0:0
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_3_POSITION       19
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_3_FMASK  64'b0000000000000000000000000000000000000000000010000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_3_HW_LD_MASK     64'b0000000000000000000000000000000000000000000010000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_3_POR_VALUE      1'b0
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_2_FID    6
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_2_SLC    18:18
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_2_WIDTH  1
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_2_INT_SLC        0:0
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_2_POSITION       18
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_2_FMASK  64'b0000000000000000000000000000000000000000000001000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_2_HW_LD_MASK     64'b0000000000000000000000000000000000000000000001000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_2_POR_VALUE      1'b0
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_1_FID    7
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_1_SLC    17:17
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_1_WIDTH  1
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_1_INT_SLC        0:0
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_1_POSITION       17
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_1_FMASK  64'b0000000000000000000000000000000000000000000000100000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_1_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000100000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_1_POR_VALUE      1'b0
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_0_FID    8
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_0_SLC    16:16
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_0_WIDTH  1
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_0_INT_SLC        0:0
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_0_POSITION       16
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_0_FMASK  64'b0000000000000000000000000000000000000000000000010000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_0_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000010000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_0_POR_VALUE      1'b0
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_FID   9
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_SLC   15:8
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_WIDTH 8
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_INT_SLC       7:0
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_POSITION      8
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_FMASK 64'b0000000000000000000000000000000000000000000000001111111100000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000001111111100000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_POR_VALUE     8'b00000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_STATUS_FID    10
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_STATUS_SLC    7:0
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_STATUS_WIDTH  8
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_STATUS_INT_SLC        7:0
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_STATUS_POSITION       0
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_STATUS_FMASK  64'b0000000000000000000000000000000000000000000000000000000011111111
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_STATUS_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_STATUS_POR_VALUE      8'b00000000


`endif