// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: dmu_mmu_csr_ctl_entry.v
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// ========== Copyright Header End ============================================
module dmu_mmu_csr_ctl_entry
// synopsys translate_off
//====================================================================
//====================================================================
// synopsys translate_off
input omni_ld; // Omni load
// vlint flag_input_port_not_connected off
input [`FIRE_DLC_MMU_CSR_CTL_WIDTH - 1:0] omni_data; // Omni write data
// vlint flag_input_port_not_connected on
input clk; // Clock signal
input rst_l; // Reset signal
// vlint flag_input_port_not_connected off
input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
// vlint flag_input_port_not_connected on
output [`FIRE_DLC_MMU_CSR_CTL_WIDTH-1:0] ctl_csrbus_read_data; // SW read data
input [`FIRE_DLC_MMU_CSR_CTL_SPARES_INT_SLC] ctl_spares_hw_write;
// data bus for hw loading of ctl_spares.
input ctl_paq_hw_write; // data bus for hw loading of ctl_paq.
input ctl_vaq_hw_write; // data bus for hw loading of ctl_vaq.
input ctl_tpl_hw_write; // data bus for hw loading of ctl_tpl.
input ctl_tip_hw_write; // data bus for hw loading of ctl_tip.
input [`FIRE_DLC_MMU_CSR_CTL_TCM_INT_SLC] ctl_tcm_hw_write; // data bus for hw
//====================================================================
//====================================================================
// synopsys translate_off
wire omni_ld; // Omni load
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
wire [`FIRE_DLC_MMU_CSR_CTL_WIDTH - 1:0] omni_data; // Omni write data
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire clk; // Clock signal
wire rst_l; // Reset signal
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire [`FIRE_DLC_MMU_CSR_CTL_WIDTH-1:0] ctl_csrbus_read_data; // SW read data
wire [`FIRE_DLC_MMU_CSR_CTL_SPARES_INT_SLC] ctl_spares_hw_write; // data bus
wire ctl_paq_hw_write; // data bus for hw loading of ctl_paq.
wire ctl_vaq_hw_write; // data bus for hw loading of ctl_vaq.
wire ctl_tpl_hw_write; // data bus for hw loading of ctl_tpl.
wire ctl_tip_hw_write; // data bus for hw loading of ctl_tip.
wire [`FIRE_DLC_MMU_CSR_CTL_TCM_INT_SLC] ctl_tcm_hw_write; // data bus for hw
//====================================================================
//====================================================================
wire [3:0] reset_spares = 4'h0;
wire [0:0] reset_paq = 1'h0;
wire [0:0] reset_vaq = 1'h0;
wire [0:0] reset_tpl = 1'h0;
wire [0:0] reset_tip = 1'h0;
wire [1:0] reset_tcm = 2'h0;
wire [3:0] reset_sparec = 4'h0;
wire [0:0] reset_pd = 1'h0;
wire [0:0] reset_se = 1'h0;
wire [1:0] reset_cm = 2'h0;
wire [0:0] reset_busid_sel = 1'h0;
wire [0:0] reset_sun4v_en = 1'h0;
wire [0:0] reset_be = 1'h0;
wire [0:0] reset_te = 1'h0;
//----- Active high reset wires
wire rst_l_active_high = ~rst_l;
//====================================================
// Instantiation of flops
//====================================================
// synopsys translate_off
.omni_data (omni_data[0]),
.rst (rst_l_active_high),
.csr_data (csrbus_wr_data[0]),
.q (ctl_csrbus_read_data[0])
// synopsys translate_off
.omni_data (omni_data[1]),
.rst (rst_l_active_high),
.csr_data (csrbus_wr_data[1]),
.q (ctl_csrbus_read_data[1])
// synopsys translate_off
.omni_data (omni_data[2]),
.rst (rst_l_active_high),
.rst_val (reset_sun4v_en[0]),
.csr_data (csrbus_wr_data[2]),
.q (ctl_csrbus_read_data[2])
// synopsys translate_off
.omni_data (omni_data[3]),
.rst (rst_l_active_high),
.rst_val (reset_busid_sel[0]),
.csr_data (csrbus_wr_data[3]),
.q (ctl_csrbus_read_data[3])
assign ctl_csrbus_read_data[4] = 1'b0; // bit 4
assign ctl_csrbus_read_data[5] = 1'b0; // bit 5
assign ctl_csrbus_read_data[6] = 1'b0; // bit 6
assign ctl_csrbus_read_data[7] = 1'b0; // bit 7
// synopsys translate_off
.omni_data (omni_data[8]),
.rst (rst_l_active_high),
.csr_data (csrbus_wr_data[8]),
.q (ctl_csrbus_read_data[8])
// synopsys translate_off
.omni_data (omni_data[9]),
.rst (rst_l_active_high),
.csr_data (csrbus_wr_data[9]),
.q (ctl_csrbus_read_data[9])
// synopsys translate_off
.omni_data (omni_data[10]),
.rst (rst_l_active_high),
.csr_data (csrbus_wr_data[10]),
.q (ctl_csrbus_read_data[10])
assign ctl_csrbus_read_data[11] = 1'b0; // bit 11
// synopsys translate_off
.omni_data (omni_data[12]),
.rst (rst_l_active_high),
.csr_data (csrbus_wr_data[12]),
.q (ctl_csrbus_read_data[12])
assign ctl_csrbus_read_data[13] = 1'b0; // bit 13
assign ctl_csrbus_read_data[14] = 1'b0; // bit 14
assign ctl_csrbus_read_data[15] = 1'b0; // bit 15
// synopsys translate_off
.omni_data (omni_data[16]),
.rst (rst_l_active_high),
.rst_val (reset_sparec[0]),
.csr_data (csrbus_wr_data[16]),
.q (ctl_csrbus_read_data[16])
// synopsys translate_off
.omni_data (omni_data[17]),
.rst (rst_l_active_high),
.rst_val (reset_sparec[1]),
.csr_data (csrbus_wr_data[17]),
.q (ctl_csrbus_read_data[17])
// synopsys translate_off
.omni_data (omni_data[18]),
.rst (rst_l_active_high),
.rst_val (reset_sparec[2]),
.csr_data (csrbus_wr_data[18]),
.q (ctl_csrbus_read_data[18])
// synopsys translate_off
.omni_data (omni_data[19]),
.rst (rst_l_active_high),
.rst_val (reset_sparec[3]),
.csr_data (csrbus_wr_data[19]),
.q (ctl_csrbus_read_data[19])
assign ctl_csrbus_read_data[20] = 1'b0; // bit 20
assign ctl_csrbus_read_data[21] = 1'b0; // bit 21
assign ctl_csrbus_read_data[22] = 1'b0; // bit 22
assign ctl_csrbus_read_data[23] = 1'b0; // bit 23
assign ctl_csrbus_read_data[24] = 1'b0; // bit 24
assign ctl_csrbus_read_data[25] = 1'b0; // bit 25
assign ctl_csrbus_read_data[26] = 1'b0; // bit 26
assign ctl_csrbus_read_data[27] = 1'b0; // bit 27
assign ctl_csrbus_read_data[28] = 1'b0; // bit 28
assign ctl_csrbus_read_data[29] = 1'b0; // bit 29
assign ctl_csrbus_read_data[30] = 1'b0; // bit 30
assign ctl_csrbus_read_data[31] = 1'b0; // bit 31
assign ctl_csrbus_read_data[32] = 1'b0; // bit 32
assign ctl_csrbus_read_data[33] = 1'b0; // bit 33
assign ctl_csrbus_read_data[34] = 1'b0; // bit 34
assign ctl_csrbus_read_data[35] = 1'b0; // bit 35
assign ctl_csrbus_read_data[36] = 1'b0; // bit 36
assign ctl_csrbus_read_data[37] = 1'b0; // bit 37
assign ctl_csrbus_read_data[38] = 1'b0; // bit 38
assign ctl_csrbus_read_data[39] = 1'b0; // bit 39
// synopsys translate_off
.rst (rst_l_active_high),
.hw_data (ctl_tcm_hw_write[0]),
.q (ctl_csrbus_read_data[40])
// synopsys translate_off
.rst (rst_l_active_high),
.hw_data (ctl_tcm_hw_write[1]),
.q (ctl_csrbus_read_data[41])
// synopsys translate_off
.rst (rst_l_active_high),
.hw_data (ctl_tip_hw_write),
.q (ctl_csrbus_read_data[42])
// synopsys translate_off
.rst (rst_l_active_high),
.hw_data (ctl_tpl_hw_write),
.q (ctl_csrbus_read_data[43])
// synopsys translate_off
.rst (rst_l_active_high),
.hw_data (ctl_vaq_hw_write),
.q (ctl_csrbus_read_data[44])
// synopsys translate_off
.rst (rst_l_active_high),
.hw_data (ctl_paq_hw_write),
.q (ctl_csrbus_read_data[45])
assign ctl_csrbus_read_data[46] = 1'b0; // bit 46
assign ctl_csrbus_read_data[47] = 1'b0; // bit 47
// synopsys translate_off
.rst (rst_l_active_high),
.rst_val (reset_spares[0]),
.hw_data (ctl_spares_hw_write[0]),
.q (ctl_csrbus_read_data[48])
// synopsys translate_off
.rst (rst_l_active_high),
.rst_val (reset_spares[1]),
.hw_data (ctl_spares_hw_write[1]),
.q (ctl_csrbus_read_data[49])
// synopsys translate_off
.rst (rst_l_active_high),
.rst_val (reset_spares[2]),
.hw_data (ctl_spares_hw_write[2]),
.q (ctl_csrbus_read_data[50])
// synopsys translate_off
.rst (rst_l_active_high),
.rst_val (reset_spares[3]),
.hw_data (ctl_spares_hw_write[3]),
.q (ctl_csrbus_read_data[51])
assign ctl_csrbus_read_data[52] = 1'b0; // bit 52
assign ctl_csrbus_read_data[53] = 1'b0; // bit 53
assign ctl_csrbus_read_data[54] = 1'b0; // bit 54
assign ctl_csrbus_read_data[55] = 1'b0; // bit 55
assign ctl_csrbus_read_data[56] = 1'b0; // bit 56
assign ctl_csrbus_read_data[57] = 1'b0; // bit 57
assign ctl_csrbus_read_data[58] = 1'b0; // bit 58
assign ctl_csrbus_read_data[59] = 1'b0; // bit 59
assign ctl_csrbus_read_data[60] = 1'b0; // bit 60
assign ctl_csrbus_read_data[61] = 1'b0; // bit 61
assign ctl_csrbus_read_data[62] = 1'b0; // bit 62
assign ctl_csrbus_read_data[63] = 1'b0; // bit 63
endmodule // dmu_mmu_csr_ctl_entry