// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: mcu_rdpctl_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
`define DRIF_MCU_STATE_00 5'd0
`define DRIF_MCU_STATE_01 5'd1
`define DRIF_MCU_STATE_02 5'd2
`define DRIF_MCU_STATE_03 5'd3
`define DRIF_MCU_STATE_04 5'd4
`define DRIF_MCU_STATE_05 5'd5
`define DRIF_MCU_STATE_06 5'd6
`define DRIF_MCU_STATE_07 5'd7
`define DRIF_MCU_STATE_08 5'd8
`define DRIF_MCU_STATE_09 5'd9
`define DRIF_MCU_STATE_10 5'd10
`define DRIF_MCU_STATE_11 5'd11
`define DRIF_MCU_STATE_12 5'd12
`define DRIF_MCU_STATE_13 5'd13
`define DRIF_MCU_STATE_14 5'd14
`define DRIF_MCU_STATE_15 5'd15
`define DRIF_MCU_STATE_16 5'd16
`define DRIF_MCU_STATE_17 5'd17
`define DRIF_MCU_STATE_18 5'd18
`define DRIF_MCU_STATE_19 5'd19
`define DRIF_MCU_STATE_20 5'd20
`define DRIF_MCU_STATE_21 5'd21
`define DRIF_MCU_STATE_22 5'd22
`define DRIF_MCU_STATE_23 5'd23
`define DRIF_MCU_STATE_24 5'd24
`define DRIF_MCU_STATE_25 5'd25
`define DRIF_MCU_STATE_26 5'd26
`define DRIF_MCU_STATE_MAX 4
`define DRIF_MCU_STATE_WIDTH 5
`define UCB_READ_NACK 4'b0000 // ack/nack types
`define UCB_READ_ACK 4'b0001
`define UCB_WRITE_ACK 4'b0010
`define UCB_IFILL_ACK 4'b0011
`define UCB_IFILL_NACK 4'b0111
`define UCB_READ_REQ 4'b0100 // req types
`define UCB_WRITE_REQ 4'b0101
`define UCB_IFILL_REQ 4'b0110
`define UCB_INT 4'b1000 // plain interrupt
`define UCB_INT_VEC 4'b1100 // interrupt with vector
`define UCB_RESET_VEC 4'b1101 // reset with vector
`define UCB_IDLE_VEC 4'b1110 // idle with vector
`define UCB_RESUME_VEC 4'b1111 // resume with vector
// UCB Data Packet Format
// ======================
`define UCB_NOPAY_PKT_WIDTH 64 // packet without payload
`define UCB_64PAY_PKT_WIDTH 128 // packet with 64 bit payload
`define UCB_128PAY_PKT_WIDTH 192 // packet with 128 bit payload
`define UCB_DATA_EXT_HI 191 // (64) extended data
`define UCB_DATA_EXT_LO 128
`define UCB_DATA_HI 127 // (64) data
`define UCB_RSV_HI 63 // (9) reserved bits
`define UCB_ADDR_HI 54 // (40) bit address
`define UCB_SIZE_HI 14 // (3) request size
`define UCB_BUF_HI 11 // (2) buffer ID
`define UCB_THR_HI 9 // (6) cpu/thread ID
`define UCB_PKT_HI 3 // (4) packet type
`define UCB_DATA_EXT_WIDTH 64
`define UCB_DATA_WIDTH 64
`define UCB_ADDR_WIDTH 40
// Size encoding for the UCB_SIZE_HI/LO field
`define UCB_SIZE_1B 3'b000
`define UCB_SIZE_2B 3'b001
`define UCB_SIZE_4B 3'b010
`define UCB_SIZE_8B 3'b011
`define UCB_SIZE_16B 3'b100
// UCB Interrupt Packet Format
// ===========================
`define UCB_INT_PKT_WIDTH 64
`define UCB_INT_RSV_HI 63 // (7) reserved bits
`define UCB_INT_RSV_LO 57
`define UCB_INT_VEC_HI 56 // (6) interrupt vector
`define UCB_INT_VEC_LO 51
`define UCB_INT_STAT_HI 50 // (32) interrupt status
`define UCB_INT_STAT_LO 19
`define UCB_INT_DEV_HI 18 // (9) device ID
`define UCB_INT_DEV_LO 10
//`define UCB_THR_HI 9 // (6) cpu/thread ID shared with
//`define UCB_THR_LO 4 data packet format
//`define UCB_PKT_HI 3 // (4) packet type shared with
//`define UCB_PKT_LO 0 // data packet format
`define UCB_INT_RSV_WIDTH 7
`define UCB_INT_VEC_WIDTH 6
`define UCB_INT_STAT_WIDTH 32
`define UCB_INT_DEV_WIDTH 9
`define MCU_CAS_BIT2_SEL_PA10 4'h1
`define MCU_CAS_BIT2_SEL_PA32 4'h2
`define MCU_CAS_BIT2_SEL_PA33 4'h4
`define MCU_CAS_BIT2_SEL_PA34 4'h8
`define MCU_CAS_BIT3_SEL_PA11 4'h1
`define MCU_CAS_BIT3_SEL_PA33 4'h2
`define MCU_CAS_BIT3_SEL_PA34 4'h4
`define MCU_CAS_BIT3_SEL_PA35 4'h8
`define MCU_CAS_BIT4_SEL_PA12 3'h1
`define MCU_CAS_BIT4_SEL_PA35 3'h2
`define MCU_CAS_BIT4_SEL_PA36 3'h4
`define MCU_DIMMHI_SEL_ZERO 6'h01
`define MCU_DIMMHI_SEL_PA32 6'h02
`define MCU_DIMMHI_SEL_PA33 6'h04
`define MCU_DIMMHI_SEL_PA34 6'h08
`define MCU_DIMMHI_SEL_PA35 6'h10
`define MCU_DIMMHI_SEL_PA36 6'h20
`define MCU_DIMMLO_SEL_ZERO 4'h1
`define MCU_DIMMLO_SEL_PA10 4'h2
`define MCU_DIMMLO_SEL_PA11 4'h4
`define MCU_DIMMLO_SEL_PA12 4'h8
`define MCU_RANK_SEL_ZERO 7'h01
`define MCU_RANK_SEL_PA32 7'h02
`define MCU_RANK_SEL_PA33 7'h04
`define MCU_RANK_SEL_PA34 7'h08
`define MCU_RANK_SEL_PA35 7'h10
`define MCU_RANK_SEL_PA10 7'h20
`define MCU_RANK_SEL_PA11 7'h40
`define MCU_ADDR_ERR_SEL_39_32 6'h01
`define MCU_ADDR_ERR_SEL_39_33 6'h02
`define MCU_ADDR_ERR_SEL_39_34 6'h04
`define MCU_ADDR_ERR_SEL_39_35 6'h08
`define MCU_ADDR_ERR_SEL_39_36 6'h10
`define MCU_ADDR_ERR_SEL_39_37 6'h20
`define DRIF_ERR_IDLE_ST 5'h1
`define DRIF_ERR_READ0_ST 5'h2
`define DRIF_ERR_WRITE_ST 5'h4
`define DRIF_ERR_READ1_ST 5'h8
`define DRIF_ERR_CRC_FR 4
`define DRIF_ERR_CRC_FR_ST 5'h10
`define MCU_WDQ_RF_DATA_WIDTH 72
`define MCU_WDQ_RF_ADDR_WIDTH 5
`define MCU_WDQ_RF_DEPTH 32
`define FBD_TS0_HDR 12'hbfe
`define FBD_TS1_HDR 12'hffe
`define FBD_TS2_HDR 12'h7fe
`define FBD_TS3_HDR 12'h3fe
// MCU FBDIMM Channel commands
`define FBD_DRAM_CMD_NOP 3'h0
`define FBD_DRAM_CMD_OTHER 3'h1
`define FBD_DRAM_CMD_RD 3'h2
`define FBD_DRAM_CMD_WR 3'h3
`define FBD_DRAM_CMD_ACT 3'h4
`define FBD_DRAM_CMD_WDATA 3'h5
`define FBD_DRAM_CMD_OTHER_REF 3'h5
`define FBD_DRAM_CMD_OTHER_SRE 3'h4
`define FBD_DRAM_CMD_OTHER_PDE 3'h2
`define FBD_DRAM_CMD_OTHER_SRPDX 3'h3
`define FBD_CHNL_CMD_NOP 2'h0
`define FBD_CHNL_CMD_SYNC 2'h1
`define FBD_CHNL_CMD_SCRST 2'h2
`define FBDIC_ERR_IDLE_ST 7'h01
`define FBDIC_ERR_STS_ST 7'h02
`define FBDIC_ERR_SCRST_ST 7'h04
`define FBDIC_ERR_SCRST 2
`define FBDIC_ERR_SCRST_STS_ST 7'h08
`define FBDIC_ERR_SCRST_STS 3
`define FBDIC_ERR_STS2_ST 7'h10
`define FBDIC_ERR_FASTRST_ST 7'h20
`define FBDIC_ERR_FASTRST 5
`define FBDIC_ERR_FASTRST_STS_ST 7'h40
`define FBDIC_ERR_FASTRST_STS 6
`define IBTX_STATE_IDLE 0
`define IBTX_STATE_PATT 1
`define IBTX_STATE_MODN 2
`define IBTX_STATE_CONST 3
`define IBRX_STATE_IDLE 0
`define IBRX_STATE_PATT 1
`define IBRX_STATE_MODN 2
`define IBRX_STATE_CONST 3
rdpctl0_dummy_data_valid,
rdpctl1_dummy_data_valid,
fbdic_chnl_reset_error_mode,
drif_single_channel_mode,
l2if0_rd_dummy_req_addr5,
l2if1_rd_dummy_req_addr5,
wire ff_dummy_req0_scanin;
wire ff_dummy_req0_scanout;
wire rdpctl0_rd_dummy_req_en;
wire rdpctl0_rd_dummy_req_addr5_in;
wire [2:0] rdpctl0_rd_dummy_req_id_in;
wire rdpctl0_rd_dummy_addr_err_in;
wire ff_dummy_req1_scanin;
wire ff_dummy_req1_scanout;
wire rdpctl1_rd_dummy_req_en;
wire rdpctl1_rd_dummy_req_addr5_in;
wire [2:0] rdpctl1_rd_dummy_req_id_in;
wire rdpctl1_rd_dummy_addr_err_in;
wire ff_ddp_data_valid_scanin;
wire ff_ddp_data_valid_scanout;
wire rdpctl_mcu_data_valid;
wire [35:0] rdpctl0_ecc_loc;
wire [35:0] rdpctl1_ecc_loc;
wire rdpctl0_dummy_data_valid_in;
wire rdpctl1_dummy_data_valid_in;
wire ff_data_cnt_scanout;
wire rdpctl_fifo_err_crc;
wire [19:0] rdpctl_fifo_ent0;
wire rdpctl_fifo_err_xaction;
wire rdpctl_fifo_rank_adr;
wire [2:0] rdpctl_fifo_dimm_adr;
wire [2:0] rdpctl_fifo_bank_adr;
wire rdpctl_fifo_addr_pa_err;
wire rdpctl_fifo_err_type;
wire rdpctl_fifo_addr_parity;
wire [2:0] rdpctl_fifo_rd_index;
wire [2:0] rdpctl_fifo_rd_req_id;
wire rdpctl_fifo_err_xactnum;
wire rdpctl_fifo_qword_id;
wire rdpctl_fifo_addr_parity_p1;
wire rdpctl_clear_drq_entry;
wire rdpctl_fifo_scrub_d1;
wire rdpctl_fifo_err_xaction_d1;
wire rdpctl_crc_error_d1;
wire drif_err_state_crc_fr_d1;
wire rdpctl_clear_drq0_entry;
wire rdpctl_fifo_l2bank_d1;
wire rdpctl_clear_drq1_entry;
wire [7:0] rdpctl_drq0_clear_ent_in;
wire [2:0] rdpctl_fifo_rd_index_d1;
wire [7:0] rdpctl_drq1_clear_ent_in;
wire ff_drif_clear_ent_scanin;
wire ff_drif_clear_ent_scanout;
wire rdpctl_l2t0_data_valid_in;
wire rdpctl_crc_error_in;
wire rdpctl_l2t1_data_valid_in;
wire rdpctl_l2t_data_valid;
wire ff_l2t_data_valid_scanin;
wire ff_l2t_data_valid_scanout;
wire rdpctl_scrub_data_valid_in;
wire ff_scrub_data_valid_scanin;
wire ff_scrub_data_valid_scanout;
wire rdpctl_scrub_data_valid_out;
wire rdpctl_scrub_data_valid;
wire rdpctl0_rd_dummy_req_addr5;
wire rdpctl1_rd_dummy_req_addr5;
wire ff_qword_id_scanout;
wire [2:0] rdpctl_rd_req_id_in;
wire [2:0] rdpctl0_rd_dummy_req_id;
wire [2:0] rdpctl1_rd_dummy_req_id;
wire ff_rd_req_id_scanin;
wire ff_rd_req_id_scanout;
wire rdpctl0_rd_dummy_addr_err;
wire rdpctl1_rd_dummy_addr_err;
wire [1:0] rdpctl_rddata_state;
wire rdpctl_crc_err_st0_d1;
wire rdpctl_crc_err_st1_d1;
wire rdpctl_crc_err_st2_d1;
wire ff_crc_err_dly_scanin;
wire ff_crc_err_dly_scanout;
wire readdp_ecc_multi_err_d1_in;
wire ff_mecc_errors_scanin;
wire ff_mecc_errors_scanout;
wire readdp_ecc_multi_err_d1;
wire readdp_ecc_multi_err_d2;
wire readdp_ecc_multi_err_d3;
wire rdpctl_ecc_multi_err;
wire [1:0] rdpctl_ecc_multi_err_d1;
wire rdpctl_ecc_single_err;
wire [1:0] rdpctl_ecc_single_err_d1;
wire rdpctl_fifo_err_crc_d1;
wire [13:0] rdpctl_err_fifo_data_in;
wire ff_err_fifo_data_scanin;
wire ff_err_fifo_data_scanout;
wire ff_fifo_deq_d1_scanin;
wire ff_fifo_deq_d1_scanout;
wire rdpctl_fifo_err_type_d1;
wire rdpctl_fifo_err_xactnum_d1;
wire rdpctl_meu_error_en;
wire rdpctl_meu_error_in;
wire pff_err_sts_bit63_wmr_scanin;
wire pff_err_sts_bit63_wmr_scanout;
wire rdpctl_mec_error_en;
wire rdpctl_mec_error_in;
wire pff_err_sts_bit62_wmr_scanin;
wire pff_err_sts_bit62_wmr_scanout;
wire rdpctl_dac_error_en;
wire rdpctl_dac_error_in;
wire pff_err_sts_bit61_wmr_scanin;
wire pff_err_sts_bit61_wmr_scanout;
wire rdpctl_dau_error_en;
wire rdpctl_dau_error_in;
wire pff_err_sts_bit60_wmr_scanin;
wire pff_err_sts_bit60_wmr_scanout;
wire rdpctl_dsc_error_en;
wire rdpctl_dsc_error_in;
wire pff_err_sts_bit59_wmr_scanin;
wire pff_err_sts_bit59_wmr_scanout;
wire rdpctl_dsu_error_en;
wire rdpctl_dsu_error_in;
wire pff_err_sts_bit58_wmr_scanin;
wire pff_err_sts_bit58_wmr_scanout;
wire rdpctl_dbu_error_en;
wire rdpctl_dbu_error_in;
wire pff_err_sts_bit57_wmr_scanin;
wire pff_err_sts_bit57_wmr_scanout;
wire rdpctl_meb_error_en;
wire rdpctl_meb_error_in;
wire pff_err_sts_bit56_wmr_scanin;
wire pff_err_sts_bit56_wmr_scanout;
wire rdpctl_fbu_error_en;
wire rdpctl_fbu_error_in;
wire pff_err_sts_bit55_wmr_scanin;
wire pff_err_sts_bit55_wmr_scanout;
wire ff_fbd_unrecov_err_scanin;
wire ff_fbd_unrecov_err_scanout;
wire rdpctl_fbd_unrecov_err_1_in;
wire rdpctl_crc_unrecov_err_in;
wire ff_crc_unrecov_err_scanin;
wire ff_crc_unrecov_err_scanout;
wire rdpctl_fbr_error_en;
wire rdpctl_fbr_error_in;
wire pff_err_sts_bit54_wmr_scanin;
wire pff_err_sts_bit54_wmr_scanout;
wire rdpctl_fbd0_recov_err_in;
wire rdpctl_fbd1_recov_err_in;
wire ff_fbd_recov_err_scanin;
wire ff_fbd_recov_err_scanout;
wire rdpctl_crc_recov_err_in;
wire ff_crc_recov_err_scanin;
wire ff_crc_recov_err_scanout;
wire rdpctl_crc_recov_err_out;
wire [15:0] rdpctl0_syndrome;
wire [15:0] rdpctl1_syndrome;
wire rdpctl_err_sts_reg_en;
wire [15:0] rdpctl_err_sts_reg_in;
wire pff_err_syn_wmr_scanin;
wire pff_err_syn_wmr_scanout;
wire rdpctl_err_retry_ld_en;
wire rdpctl_err_retry_ld_clr;
wire ff_err_retry_ld_scanin;
wire ff_err_retry_ld_scanout;
wire rdpctl_err_retry_ld_out;
wire rdpctl_err_retry_ld;
wire rdpctl_retry_reg_valid;
wire [17:0] rdpctl_err_retry2_reg;
wire [17:0] rdpctl_err_retry1_reg;
wire rdpctl_err_retry1_reg_en;
wire [17:0] rdpctl_err_retry1_reg_in;
wire [15:0] rdpctl_retry_syndrome;
wire pff_err_retry1_wmr_scanin;
wire pff_err_retry1_wmr_scanout;
wire rdpctl_err_retry2_reg_en;
wire [17:0] rdpctl_err_retry2_reg_in;
wire pff_err_retry2_wmr_scanin;
wire pff_err_retry2_wmr_scanout;
wire rdpctl_err_retry2_reg_en_no_ld;
wire rdpctl_err_retry1_reg_en_no_ld;
wire rdpctl_retry_reg_valid_in;
wire rdpctl_retry_reg_valid_en;
wire pff_retry_reg_valid_wmr_scanin;
wire pff_retry_reg_valid_wmr_scanout;
wire rdpctl_syndrome_dly_en;
wire ff_syndrome_dly_scanin;
wire ff_syndrome_dly_scanout;
wire [15:0] rdpctl0_syndrome_d1;
wire [15:0] rdpctl1_syndrome_d1;
wire rdpctl_err_addr_reg_en;
wire [35:0] rdpctl_err_addr_reg_in;
wire [35:0] rdpctl_err_addr;
wire [1:0] rdpctl_scrub_data_cnt;
wire pff_err_addr_reg_wmr_scanin;
wire pff_err_addr_reg_wmr_scanout;
wire [1:1] rdpctl_scrub_data_cnt_in;
wire rdpctl_scrub_data_cnt_en;
wire ff_scrub_data_cnt_scanin;
wire ff_scrub_data_cnt_scanout;
wire [15:0] rdpctl_secc_cnt;
wire rdpctl_secc_cnt_intr_in;
wire pff_secc_int_en_wmr_scanin;
wire pff_secc_int_en_wmr_scanout;
wire rdpctl_secc_int_enabled;
wire [15:0] rdpctl_secc_cnt_next;
wire [15:0] rdpctl_secc_cnt_in;
wire pff_secc_cnt_wmr_scanin;
wire pff_secc_cnt_wmr_scanout;
wire ff_secc_cnt_intr_scanin;
wire ff_secc_cnt_intr_scanout;
wire [5:1] rdpctl_dbg_trig_enable_in;
wire pff_dbg_trig_wmr_scanin;
wire pff_dbg_trig_wmr_scanout;
wire [35:0] rdpctl_err_loc_in;
wire pff_err_loc_wmr_scanin;
wire pff_err_loc_wmr_scanout;
wire rdpctl_scrb0_err_valid_in;
wire rdpctl_scrb1_err_valid_in;
wire ff_scrub_ecc_err_scanin;
wire ff_scrub_ecc_err_scanout;
wire ff_rd_dummy_req0_scanin;
wire ff_rd_dummy_req0_scanout;
wire rdpctl0_rd_dummy_req;
wire ff_rd_dummy0_scanin;
wire ff_rd_dummy0_scanout;
wire ff_rd_dummy_req1_scanin;
wire ff_rd_dummy_req1_scanout;
wire rdpctl1_rd_dummy_req;
wire ff_rd_dummy1_scanin;
wire ff_rd_dummy1_scanout;
wire rdpctl_dummy_priority_in;
wire rdpctl_dummy_priority;
wire ff_dummy_priority_scanin;
wire ff_dummy_priority_scanout;
wire ff_dummy_data_valid_scanin;
wire ff_dummy_data_valid_scanout;
wire rdpctl_scrub_wren_out;
wire rdpctl_scrub_wren_in;
wire ff_scrub_wren_scanin;
wire ff_scrub_wren_scanout;
wire [1:0] rdpctl_rddata_state_in;
wire ff_rddata_state_scanin;
wire ff_rddata_state_scanout;
wire ff_err_ecci_scanout;
output rdpctl_scrub_addrinc_en; // increment scrub address
// error registers to drif block for read access
output [35:0] rdpctl_err_addr_reg;
output [25:0] rdpctl_err_sts_reg;
output [35:0] rdpctl_err_loc;
output [15:0] rdpctl_err_cnt;
output [36:0] rdpctl_err_retry_reg;
output rdpctl_dbg_trig_enable; // debug mode trigger enable
// clear entries from read queues when dequeued from rdpctl fifo if no errors
output [7:0] rdpctl_drq0_clear_ent;
output [7:0] rdpctl_drq1_clear_ent;
// error information to drif for error retries
output rdpctl_err_fifo_enq;
output [14:0] rdpctl_err_fifo_data;
output rdpctl_fifo_empty;
output rdpctl_no_crc_err;
output rdpctl_fbd0_recov_err;
output rdpctl_fbd1_recov_err;
output [1:0] rdpctl_fbd_unrecov_err;
output rdpctl_crc_recov_err;
output rdpctl_crc_unrecov_err;
output rdpctl_scrub_read_done; // resets outstanding scrub flop
output rdpctl_scrb0_err_valid;
output rdpctl_scrb1_err_valid;
output rdpctl_l2t0_data_valid; // data valid signal to rdata_ctl for L2 0
output rdpctl_l2t1_data_valid; // data valid signal to rdata_ctl for L2 1
output rdpctl_qword_id; // quad-word id for returning data sub-packet
output [2:0] rdpctl_rd_req_id; // read request id for returning data packet
output rdpctl_pa_err; // physical address error bit to OR with mecc
output rdpctl_radr_parity; // parity to readdp
output [2:0] rdpctl_rddata_en; // read data enable for single-dimm mode
output rdpctl_inj_ecc_err; // ecc error injection for readdp
// indicates to rdata block when empty is coming to respond to dummy read
output rdpctl0_dummy_data_valid;
output rdpctl1_dummy_data_valid;
output rdpctl_secc_cnt_intr; // single ecc error counter interrupt
output rdpctl_scrub_wren; // write enable for wrdp scrub data buffer
output [1:0] rdpctl_dtm_mask_chnl;
output rdpctl_dtm_atspeed;
output [1:0] rdpctl_dtm_chnl_enable;
input fbdic_rddata_vld; // read data from fbdic valid
input fbdic_chnl_reset_error;
input drif_err_state_crc_fr;
input fbdic_chnl_reset_error_mode;
input fbdic_cfgrd_crc_error;
// information associated with returning read data
input drif_send_info_val; // which send_info buses are valid
input [19:0] drif_send_info; // info for CMD A slot (rd or wr)
input [1:0] readdp_ecc_single_err; // single-bit ecc error detected
input [1:0] readdp_ecc_multi_err; // multiple-bit ecc error detected
input [15:0] readdp0_syndrome; // ecc syndrome bits for error reporting
input [15:0] readdp1_syndrome; // ecc syndrome bits for error reporting
input [35:0] readdp0_ecc_loc; // error nibble for error reporting
input [35:0] readdp1_ecc_loc; // error nibble for error reporting
input [31:0] drif_scrub_addr; // scrub address for error logging
input [1:0] mcu_id; // for scrub address in address error register,
// to indicate in which mcu error occurred
// SDRAM address generation information
input drif_single_channel_mode;
input l2if0_rd_dummy_req;
input l2if0_rd_dummy_req_addr5;
input [2:0] l2if0_rd_dummy_req_id;
input l2if0_rd_dummy_addr_err;
input l2if1_rd_dummy_req;
input l2if1_rd_dummy_req_addr5;
input [2:0] l2if1_rd_dummy_req_id;
input l2if1_rd_dummy_addr_err;
// register write interface for rdpctl
input [39:0] drif_ucb_data_39to0;
input [63:54] drif_ucb_data_63to54;
input drif_err_sts_reg_ld;
input drif_err_addr_reg_ld;
input drif_err_cnt_reg_ld;
input drif_err_loc_reg_ld;
input drif_err_retry_reg_ld;
input drif_dbg_trig_reg_ld;
assign pce_ov = tcu_pce_ov;
// 0in set_clock drl2clk -default
mcu_rdpctl_ctl_l1clkhdr_ctl_macro clkgen (
mcu_rdpctl_ctl_msff_ctl_macro__width_2 ff_pm_mcus (
.scan_in(ff_pm_mcus_scanin),
.scan_out(ff_pm_mcus_scanout),
.din({rdata_pm_1mcu,rdata_pm_2mcu}),
.dout({rdpctl_pm_1mcu,rdpctl_pm_2mcu}),
mcu_rdpctl_ctl_msff_ctl_macro__width_6 ff_dummy_req0 (
.scan_in(ff_dummy_req0_scanin),
.scan_out(ff_dummy_req0_scanout),
.din({l2if0_rd_dummy_req, l2if0_rd_dummy_req_addr5, l2if0_rd_dummy_req_id[2:0], l2if0_rd_dummy_addr_err}),
.dout({rdpctl0_rd_dummy_req_en, rdpctl0_rd_dummy_req_addr5_in, rdpctl0_rd_dummy_req_id_in[2:0], rdpctl0_rd_dummy_addr_err_in}),
mcu_rdpctl_ctl_msff_ctl_macro__width_6 ff_dummy_req1 (
.scan_in(ff_dummy_req1_scanin),
.scan_out(ff_dummy_req1_scanout),
.din({l2if1_rd_dummy_req, l2if1_rd_dummy_req_addr5, l2if1_rd_dummy_req_id[2:0], l2if1_rd_dummy_addr_err}),
.dout({rdpctl1_rd_dummy_req_en, rdpctl1_rd_dummy_req_addr5_in, rdpctl1_rd_dummy_req_id_in[2:0], rdpctl1_rd_dummy_addr_err_in}),
mcu_rdpctl_ctl_msff_ctl_macro ff_ddp_data_valid (
.scan_in(ff_ddp_data_valid_scanin),
.scan_out(ff_ddp_data_valid_scanout),
.dout(rdpctl_mcu_data_valid),
mcu_rdpctl_ctl_msff_ctl_macro__width_72 ff_ecc_loc (
.scan_in(ff_ecc_loc_scanin),
.scan_out(ff_ecc_loc_scanout),
.din({readdp0_ecc_loc[35:0],readdp1_ecc_loc[35:0]}),
.dout({rdpctl0_ecc_loc[35:0],rdpctl1_ecc_loc[35:0]}),
// This part of code controls the 16 deep FIFO that directs the data that comes back
assign rdpctl_fifo_deq = rdpctl_data_cnt & rdpctl_mcu_data_valid;
assign rdpctl_data_cnt_in = rdpctl_mcu_data_valid | rdpctl0_dummy_data_valid_in | rdpctl1_dummy_data_valid_in ?
~rdpctl_data_cnt : rdpctl_data_cnt;
mcu_rdpctl_ctl_msff_ctl_macro__width_1 ff_data_cnt (
.scan_in(ff_data_cnt_scanin),
.scan_out(ff_data_cnt_scanout),
.din(rdpctl_data_cnt_in),
// 18 - error mode transaction
// 17 - drif_rank_adr_d1 - for error retry
// 16:14 - drif_dimm_adr_d1 - for error retry
// 13:11 - drif_bank_adr_d1[2:0] - for error retry
// 10 - drif_addr_err_d1 - out of bound error
// 9 - drif_addr_parity_d1
// 8 - drif_scrub_picked_d1
// 7:5 - drif_rd_index_d1[2:0] - index to free
// 4:2 - drif_rd_req_id_d1[2:0]
// 1 - drif_cas_adr_d1[1] - qword_id (PA[5])
// 0 - drif1_rd_picked_d1 - return to l2t1
assign rdpctl_fifo_err_crc = rdpctl_fifo_ent0[19];
assign rdpctl_fifo_err_xaction = rdpctl_fifo_ent0[18];
assign rdpctl_fifo_rank_adr = rdpctl_fifo_ent0[17];
assign rdpctl_fifo_dimm_adr[2:0] = rdpctl_fifo_ent0[16:14];
assign rdpctl_fifo_bank_adr[2:0] = rdpctl_fifo_ent0[13:11];
assign rdpctl_fifo_addr_pa_err = rdpctl_fifo_ent0[10] & ~rdpctl_fifo_err_xaction;
assign rdpctl_fifo_err_type = rdpctl_fifo_ent0[10] & rdpctl_fifo_err_xaction;
assign rdpctl_fifo_addr_parity = rdpctl_fifo_ent0[9];
assign rdpctl_fifo_scrub = rdpctl_fifo_ent0[8];
assign rdpctl_fifo_rd_index[2:0] = rdpctl_fifo_ent0[7:5];
assign rdpctl_fifo_rd_req_id[2:0] = rdpctl_fifo_ent0[4:2];
assign rdpctl_fifo_err_xactnum = rdpctl_fifo_ent0[2];
assign rdpctl_fifo_qword_id = rdpctl_fifo_ent0[1];
assign rdpctl_fifo_l2bank = rdpctl_fifo_ent0[0];
.otq_enq(drif_send_info_val),
.otq_din(drif_send_info[19:0]),
.otq_deq(rdpctl_fifo_deq),
.otq_dout(rdpctl_fifo_ent0[19:0]),
.next_otq_dout_9(rdpctl_fifo_addr_parity_p1),
.otq_full(rdpctl_fifo_full),
.otq_empty(rdpctl_fifo_empty),
.tcu_scan_en(tcu_scan_en)
// Clear a read entry in the Read Request Queues
assign rdpctl_clear_drq_entry = rdpctl_fifo_deq_d1 & (~rdpctl_fifo_scrub_d1 & ~rdpctl_fifo_err_xaction_d1 &
(~rdpctl_ecc_error | rdpctl_pa_err) & (~rdpctl_crc_error_d1 | drif_err_state_crc_fr_d1) |
fbdic_chnl_reset_error_mode);
assign rdpctl_clear_drq0_entry = rdpctl_clear_drq_entry & ~rdpctl_fifo_l2bank_d1;
assign rdpctl_clear_drq1_entry = rdpctl_clear_drq_entry & rdpctl_fifo_l2bank_d1;
assign rdpctl_drq0_clear_ent_in[0] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h0) & rdpctl_clear_drq0_entry;
assign rdpctl_drq0_clear_ent_in[1] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h1) & rdpctl_clear_drq0_entry;
assign rdpctl_drq0_clear_ent_in[2] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h2) & rdpctl_clear_drq0_entry;
assign rdpctl_drq0_clear_ent_in[3] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h3) & rdpctl_clear_drq0_entry;
assign rdpctl_drq0_clear_ent_in[4] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h4) & rdpctl_clear_drq0_entry;
assign rdpctl_drq0_clear_ent_in[5] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h5) & rdpctl_clear_drq0_entry;
assign rdpctl_drq0_clear_ent_in[6] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h6) & rdpctl_clear_drq0_entry;
assign rdpctl_drq0_clear_ent_in[7] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h7) & rdpctl_clear_drq0_entry;
assign rdpctl_drq1_clear_ent_in[0] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h0) & rdpctl_clear_drq1_entry;
assign rdpctl_drq1_clear_ent_in[1] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h1) & rdpctl_clear_drq1_entry;
assign rdpctl_drq1_clear_ent_in[2] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h2) & rdpctl_clear_drq1_entry;
assign rdpctl_drq1_clear_ent_in[3] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h3) & rdpctl_clear_drq1_entry;
assign rdpctl_drq1_clear_ent_in[4] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h4) & rdpctl_clear_drq1_entry;
assign rdpctl_drq1_clear_ent_in[5] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h5) & rdpctl_clear_drq1_entry;
assign rdpctl_drq1_clear_ent_in[6] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h6) & rdpctl_clear_drq1_entry;
assign rdpctl_drq1_clear_ent_in[7] = (rdpctl_fifo_rd_index_d1[2:0] == 3'h7) & rdpctl_clear_drq1_entry;
mcu_rdpctl_ctl_msff_ctl_macro__width_16 ff_drif_clear_ent (
.scan_in(ff_drif_clear_ent_scanin),
.scan_out(ff_drif_clear_ent_scanout),
.din({rdpctl_drq0_clear_ent_in[7:0],rdpctl_drq1_clear_ent_in[7:0]}),
.dout({rdpctl_drq0_clear_ent[7:0],rdpctl_drq1_clear_ent[7:0]}),
// generate data valid signals for rdata block
assign rdpctl_l2t0_data_valid_in = ~rdpctl_fifo_l2bank & ~rdpctl_fifo_scrub & ~rdpctl_fifo_err_xaction &
(~rdpctl_crc_error_in & ~rdpctl_crc_error | drif_err_state_crc_fr) &
rdpctl_mcu_data_valid | rdpctl0_dummy_data_valid_in;
assign rdpctl_l2t1_data_valid_in = rdpctl_fifo_l2bank & ~rdpctl_fifo_scrub & ~rdpctl_fifo_err_xaction &
(~rdpctl_crc_error_in & ~rdpctl_crc_error | drif_err_state_crc_fr) &
rdpctl_mcu_data_valid | rdpctl1_dummy_data_valid_in;
assign rdpctl_l2t_data_valid = rdpctl_l2t0_data_valid & ~rdpctl0_dummy_data_valid |
rdpctl_l2t1_data_valid & ~rdpctl1_dummy_data_valid;
mcu_rdpctl_ctl_msff_ctl_macro__width_2 ff_l2t_data_valid (
.scan_in(ff_l2t_data_valid_scanin),
.scan_out(ff_l2t_data_valid_scanout),
.din({rdpctl_l2t0_data_valid_in,rdpctl_l2t1_data_valid_in}),
.dout({rdpctl_l2t0_data_valid, rdpctl_l2t1_data_valid}),
assign rdpctl_scrub_data_valid_in = rdpctl_fifo_scrub & rdpctl_mcu_data_valid & ~rdpctl_fifo_err_xaction;
mcu_rdpctl_ctl_msff_ctl_macro__width_1 ff_scrub_data_valid (
.scan_in(ff_scrub_data_valid_scanin),
.scan_out(ff_scrub_data_valid_scanout),
.din(rdpctl_scrub_data_valid_in),
.dout(rdpctl_scrub_data_valid_out),
assign rdpctl_scrub_data_valid = rdpctl_scrub_data_valid_out & ~rdpctl_crc_error & ~rdpctl_crc_error_d1;
// generate qword id for rdata block
assign rdpctl_qword_id_in = (rdpctl0_dummy_data_valid_in ? rdpctl0_rd_dummy_req_addr5 :
rdpctl1_dummy_data_valid_in ? rdpctl1_rd_dummy_req_addr5 : rdpctl_fifo_qword_id) ^ rdpctl_data_cnt;
mcu_rdpctl_ctl_msff_ctl_macro__width_1 ff_qword_id (
.scan_in(ff_qword_id_scanin),
.scan_out(ff_qword_id_scanout),
.din(rdpctl_qword_id_in),
// generate read request id for rdata block
assign rdpctl_rd_req_id_in[2:0] = rdpctl0_dummy_data_valid_in ? rdpctl0_rd_dummy_req_id[2:0] :
rdpctl1_dummy_data_valid_in ? rdpctl1_rd_dummy_req_id[2:0] : rdpctl_fifo_rd_req_id[2:0];
mcu_rdpctl_ctl_msff_ctl_macro__width_3 ff_rd_req_id (
.scan_in(ff_rd_req_id_scanin),
.scan_out(ff_rd_req_id_scanout),
.din(rdpctl_rd_req_id_in[2:0]),
.dout(rdpctl_rd_req_id[2:0]),
// generate pa error bit for rdata block
assign rdpctl_pa_err_in = rdpctl0_dummy_data_valid_in ? rdpctl0_rd_dummy_addr_err :
rdpctl1_dummy_data_valid_in ? rdpctl1_rd_dummy_addr_err : rdpctl_fifo_addr_pa_err;
mcu_rdpctl_ctl_msff_ctl_macro__width_1 ff_pa_err (
.scan_in(ff_pa_err_scanin),
.scan_out(ff_pa_err_scanout),
// CRC error - nay need to drop data going to L2
assign rdpctl_crc_err_st0 = fbdic_crc_error & fbdic_rddata_vld & (rdpctl_rddata_state[1:0] == 2'h0);
assign rdpctl_crc_err_st1 = fbdic_crc_error & fbdic_rddata_vld & (rdpctl_rddata_state[1:0] == 2'h1) | rdpctl_crc_err_st0_d1;
assign rdpctl_crc_err_st2 = fbdic_crc_error & fbdic_rddata_vld & (rdpctl_rddata_state[1:0] == 2'h2) | rdpctl_crc_err_st1_d1;
assign rdpctl_crc_err_st3 = fbdic_crc_error & fbdic_rddata_vld & (rdpctl_rddata_state[1:0] == 2'h3) | rdpctl_crc_err_st2_d1;
assign rdpctl_crc_error_in = ~rdpctl_fifo_addr_pa_err &
(drif_single_channel_mode ? rdpctl_crc_err_st3 : rdpctl_crc_err_st1);
mcu_rdpctl_ctl_msff_ctl_macro__width_6 ff_crc_err_dly (
.scan_in(ff_crc_err_dly_scanin),
.scan_out(ff_crc_err_dly_scanout),
.din({ rdpctl_crc_err_st0, rdpctl_crc_err_st1, rdpctl_crc_err_st2, rdpctl_crc_error_in,
rdpctl_crc_error, drif_err_state_crc_fr}),
.dout({rdpctl_crc_err_st0_d1, rdpctl_crc_err_st1_d1, rdpctl_crc_err_st2_d1, rdpctl_crc_error,
rdpctl_crc_error_d1, drif_err_state_crc_fr_d1}),
assign rdpctl_no_crc_err = rdpctl_fifo_deq & ~rdpctl_crc_error & rdpctl_fifo_err_crc;
assign rdpctl_crc_err = rdpctl_fifo_deq & rdpctl_crc_error & rdpctl_fifo_err_crc;
// set rdpctl_ecc_error when error occurs, clear when dequeued from rdpctl fifo;
// entry will be written into error fifo in drif_ctl and error fifo's not_empty
// will disable additional requests from being issued.
assign readdp_ecc_multi_err_d1_in = |readdp_ecc_multi_err[1:0];
mcu_rdpctl_ctl_msff_ctl_macro__width_3 ff_mecc_errors (
.scan_in(ff_mecc_errors_scanin),
.scan_out(ff_mecc_errors_scanout),
.din({readdp_ecc_multi_err_d1_in,readdp_ecc_multi_err_d1,readdp_ecc_multi_err_d2}),
.dout({readdp_ecc_multi_err_d1,readdp_ecc_multi_err_d2,readdp_ecc_multi_err_d3}),
assign rdpctl_ecc_multi_err = (|readdp_ecc_multi_err[1:0]) | (|rdpctl_ecc_multi_err_d1[1:0]);
//assign readdp_ecc_single_err_d1_in = |readdp_ecc_single_err[1:0];
//msff_ctl_macro ff_secc_errors (width=3) (
// .scan_in(ff_secc_errors_scanin),
// .scan_out(ff_secc_errors_scanout),
// .din({readdp_ecc_single_err_d1_in,readdp_ecc_single_err_d1,readdp_ecc_single_err_d2}),
// .dout({readdp_ecc_single_err_d1,readdp_ecc_single_err_d2,readdp_ecc_single_err_d3}),
assign rdpctl_ecc_single_err = (|readdp_ecc_single_err[1:0]) | (|rdpctl_ecc_single_err_d1[1:0]);
assign rdpctl_ecc_error = rdpctl_ecc_multi_err | rdpctl_ecc_single_err;
assign rdpctl_err_type = rdpctl_ecc_multi_err;
// send error retry info to drif when error occurs (if it is not already a retry)
assign rdpctl_err_fifo_enq = rdpctl_fifo_deq_d1 & ((rdpctl_ecc_multi_err | rdpctl_ecc_single_err) &
~(rdpctl_fifo_err_xaction_d1 | rdpctl_crc_error_d1) |
rdpctl_crc_error_d1 & ~(rdpctl_fifo_err_crc_d1 | rdpctl_fifo_err_xaction_d1)) &
~(rdpctl_pa_err | fbdic_chnl_reset_error_mode);
assign rdpctl_err_fifo_data_in[13:0] = {rdpctl_crc_error, rdpctl_fifo_rank_adr,rdpctl_fifo_dimm_adr[2:0],
rdpctl_fifo_bank_adr[2:0], rdpctl_fifo_addr_parity, rdpctl_fifo_scrub,
rdpctl_fifo_rd_index[2:0], rdpctl_fifo_l2bank};
assign rdpctl_fifo_scrub_d1 = rdpctl_err_fifo_data[5];
assign rdpctl_fifo_rd_index_d1[2:0] = rdpctl_err_fifo_data[4:2];
assign rdpctl_fifo_l2bank_d1 = rdpctl_err_fifo_data[0];
mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_14 ff_err_fifo_data (
.scan_in(ff_err_fifo_data_scanin),
.scan_out(ff_err_fifo_data_scanout),
.din(rdpctl_err_fifo_data_in[13:0]),
.dout({rdpctl_err_fifo_data[14:2],rdpctl_err_fifo_data[0]}),
assign rdpctl_err_fifo_data[1] = ~rdpctl_crc_error;
mcu_rdpctl_ctl_msff_ctl_macro__width_5 ff_fifo_deq_d1 (
.scan_in(ff_fifo_deq_d1_scanin),
.scan_out(ff_fifo_deq_d1_scanout),
.din({rdpctl_fifo_deq,rdpctl_fifo_err_xaction,rdpctl_fifo_err_type,rdpctl_fifo_err_xactnum,
.dout({rdpctl_fifo_deq_d1,rdpctl_fifo_err_xaction_d1,rdpctl_fifo_err_type_d1,rdpctl_fifo_err_xactnum_d1,
rdpctl_fifo_err_crc_d1}),
assign rdpctl_scrub_addrinc_en = rdpctl_fifo_deq_d1 & rdpctl_fifo_scrub_d1 & ~rdpctl_ecc_error &
~rdpctl_fifo_err_xaction_d1;
// let drif know scrub is done so next scrub can be issued
assign rdpctl_scrub_read_done = rdpctl_fifo_deq_d1 & rdpctl_fifo_scrub_d1 &
~rdpctl_fifo_err_xaction_d1;
// Error type bits for error status register
assign rdpctl_err_sts_reg[25:16] = {rdpctl_meu_error, rdpctl_mec_error, rdpctl_dac_error, rdpctl_dau_error,
rdpctl_dsc_error, rdpctl_dsu_error, rdpctl_dbu_error, rdpctl_meb_error,
rdpctl_fbu_error, rdpctl_fbr_error};
// Multiple uncorrected errors
// If s/w write and error occurs in same cycle, h/w update has priority.
assign rdpctl_meu_error_en = (rdpctl_scrub_data_valid | rdpctl_l2t_data_valid) & ~rdpctl_pa_err &
((rdpctl_dau_error | rdpctl_dsu_error | rdpctl_fbu_error) & (|readdp_ecc_multi_err[1:0]) |
(&readdp_ecc_multi_err[1:0])) |
(rdpctl_dau_error | rdpctl_dsu_error | rdpctl_fbu_error) &
(drif_err_state_crc_fr & rdpctl_crc_err & rdpctl_fifo_err_crc |
fbdic_err_unrecov | fbdic_chnl_reset_error) |
assign rdpctl_meu_error_in = (rdpctl_scrub_data_valid | rdpctl_l2t_data_valid) & ~rdpctl_pa_err &
((rdpctl_dau_error | rdpctl_dsu_error | rdpctl_fbu_error) & (|readdp_ecc_multi_err[1:0]) |
(&readdp_ecc_multi_err[1:0])) |
(rdpctl_dau_error | rdpctl_dsu_error | rdpctl_fbu_error) &
(drif_err_state_crc_fr & rdpctl_crc_err & rdpctl_fifo_err_crc |
fbdic_err_unrecov | fbdic_chnl_reset_error) ? 1'b1 :
~drif_ucb_data_63to54[63] & rdpctl_meu_error;
mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_1 pff_err_sts_bit63 ( // FS:wmr_protect
.scan_in(pff_err_sts_bit63_wmr_scanin),
.scan_out(pff_err_sts_bit63_wmr_scanout),
.din(rdpctl_meu_error_in),
.en(rdpctl_meu_error_en),
// Multiple corrected errors
assign rdpctl_mec_error_en = (rdpctl_scrub_data_valid | rdpctl_l2t_data_valid) &
((rdpctl_dac_error | rdpctl_dsc_error | rdpctl_fbr_error |
rdpctl_dau_error | rdpctl_dsu_error | rdpctl_fbu_error) & (|readdp_ecc_single_err[1:0]) |
(&readdp_ecc_single_err[1:0]) |
(|readdp_ecc_single_err[1:0]) & (|readdp_ecc_multi_err[1:0])) |
(rdpctl_dac_error | rdpctl_dsc_error | rdpctl_fbr_error |
rdpctl_dau_error | rdpctl_dsu_error | rdpctl_fbu_error) &
(rdpctl_no_crc_err & rdpctl_fifo_err_crc | fbdic_err_recov) |
assign rdpctl_mec_error_in = (rdpctl_scrub_data_valid | rdpctl_l2t_data_valid) &
((rdpctl_dac_error | rdpctl_dsc_error | rdpctl_fbr_error |
rdpctl_dau_error | rdpctl_dsu_error | rdpctl_fbu_error) & (|readdp_ecc_single_err[1:0]) |
(&readdp_ecc_single_err[1:0]) |
(|readdp_ecc_single_err[1:0]) & (|readdp_ecc_multi_err[1:0])) |
(rdpctl_dac_error | rdpctl_dsc_error | rdpctl_fbr_error |
rdpctl_dau_error | rdpctl_dsu_error | rdpctl_fbu_error) &
(rdpctl_no_crc_err & rdpctl_fifo_err_crc | fbdic_err_recov) ? 1'b1 :
~drif_ucb_data_63to54[62] & rdpctl_mec_error;
mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_1 pff_err_sts_bit62 ( // FS:wmr_protect
.scan_in(pff_err_sts_bit62_wmr_scanin),
.scan_out(pff_err_sts_bit62_wmr_scanout),
.din(rdpctl_mec_error_in),
.en(rdpctl_mec_error_en),
// DRAM access correctable error
assign rdpctl_dac_error_en = rdpctl_l2t_data_valid & ~rdpctl_dac_error & (|readdp_ecc_single_err[1:0]) |
assign rdpctl_dac_error_in = rdpctl_l2t_data_valid & ~rdpctl_dac_error & (|readdp_ecc_single_err[1:0]) ? 1'b1 :
~drif_ucb_data_63to54[61] & rdpctl_dac_error;
mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_1 pff_err_sts_bit61 ( // FS:wmr_protect
.scan_in(pff_err_sts_bit61_wmr_scanin),
.scan_out(pff_err_sts_bit61_wmr_scanout),
.din(rdpctl_dac_error_in),
.en(rdpctl_dac_error_en),
// DRAM access uncorrectable error
assign rdpctl_dau_error_en = rdpctl_l2t_data_valid & ~rdpctl_dau_error & (|readdp_ecc_multi_err[1:0]) &
~rdpctl_pa_err & ~rdpctl_fbd_unrecov_err[0] | drif_err_sts_reg_ld;
assign rdpctl_dau_error_in = rdpctl_l2t_data_valid & ~rdpctl_dau_error & (|readdp_ecc_multi_err[1:0]) &
~rdpctl_pa_err & ~rdpctl_fbd_unrecov_err[0] ? 1'b1 :
~drif_ucb_data_63to54[60] & rdpctl_dau_error;
mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_1 pff_err_sts_bit60 ( // FS:wmr_protect
.scan_in(pff_err_sts_bit60_wmr_scanin),
.scan_out(pff_err_sts_bit60_wmr_scanout),
.din(rdpctl_dau_error_in),
.en(rdpctl_dau_error_en),
// Scrub access correctable error
assign rdpctl_dsc_error_en = rdpctl_scrub_data_valid & ~rdpctl_dsc_error & (|readdp_ecc_single_err[1:0]) | drif_err_sts_reg_ld;
assign rdpctl_dsc_error_in = rdpctl_scrub_data_valid & ~rdpctl_dsc_error & (|readdp_ecc_single_err[1:0]) ?
1'b1 : ~drif_ucb_data_63to54[59] & rdpctl_dsc_error;
mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_1 pff_err_sts_bit59 ( // FS:wmr_protect
.scan_in(pff_err_sts_bit59_wmr_scanin),
.scan_out(pff_err_sts_bit59_wmr_scanout),
.din(rdpctl_dsc_error_in),
.en(rdpctl_dsc_error_en),
// Scrub access uncorrectable error
assign rdpctl_dsu_error_en = rdpctl_scrub_data_valid & ~rdpctl_dsu_error & (|readdp_ecc_multi_err[1:0]) & ~rdpctl_pa_err |
assign rdpctl_dsu_error_in = rdpctl_scrub_data_valid & ~rdpctl_dsu_error & (|readdp_ecc_multi_err[1:0]) & ~rdpctl_pa_err ?
1'b1 : ~drif_ucb_data_63to54[58] & rdpctl_dsu_error;
mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_1 pff_err_sts_bit58 ( // FS:wmr_protect
.scan_in(pff_err_sts_bit58_wmr_scanin),
.scan_out(pff_err_sts_bit58_wmr_scanout),
.din(rdpctl_dsu_error_in),
.en(rdpctl_dsu_error_en),
assign rdpctl_dummy_dbu = ~rdpctl0_dummy_data_valid_in & rdpctl0_dummy_data_valid & rdpctl0_rd_dummy_addr_err |
~rdpctl1_dummy_data_valid_in & rdpctl1_dummy_data_valid & rdpctl1_rd_dummy_addr_err;
assign rdpctl_dbu_error_en = rdpctl_fifo_deq & rdpctl_fifo_addr_pa_err | rdpctl_dummy_dbu | drif_err_sts_reg_ld;
assign rdpctl_dbu_error_in = rdpctl_fifo_deq & rdpctl_fifo_addr_pa_err | rdpctl_dummy_dbu ? 1'b1 :
~drif_ucb_data_63to54[57] & rdpctl_dbu_error;
mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_1 pff_err_sts_bit57 ( // FS:wmr_protect
.scan_in(pff_err_sts_bit57_wmr_scanin),
.scan_out(pff_err_sts_bit57_wmr_scanout),
.din(rdpctl_dbu_error_in),
.en(rdpctl_dbu_error_en),
// Multiple out of bound PA error
assign rdpctl_meb_error_en = (rdpctl_fifo_deq & rdpctl_fifo_addr_pa_err | rdpctl_dummy_dbu) & rdpctl_dbu_error |
assign rdpctl_meb_error_in = (rdpctl_fifo_deq & rdpctl_fifo_addr_pa_err | rdpctl_dummy_dbu) & rdpctl_dbu_error ? 1'b1 :
~drif_ucb_data_63to54[56] & rdpctl_meb_error;
mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_1 pff_err_sts_bit56 ( // FS:wmr_protect
.scan_in(pff_err_sts_bit56_wmr_scanin),
.scan_out(pff_err_sts_bit56_wmr_scanout),
.din(rdpctl_meb_error_in),
.en(rdpctl_meb_error_en),
assign rdpctl_fbu_error_en = drif_err_state_crc_fr & rdpctl_crc_err & rdpctl_fifo_err_crc |
fbdic_err_unrecov | fbdic_chnl_reset_error | drif_err_sts_reg_ld;
assign rdpctl_fbu_error_in = drif_err_state_crc_fr & rdpctl_crc_err & rdpctl_fifo_err_crc |
fbdic_err_unrecov | fbdic_chnl_reset_error ? 1'b1 :
rdpctl_fbu_error & ~drif_ucb_data_63to54[55];
mcu_rdpctl_ctl_msff_ctl_macro__en_1 pff_err_sts_bit55 ( // FS:wmr_protect
.scan_in(pff_err_sts_bit55_wmr_scanin),
.scan_out(pff_err_sts_bit55_wmr_scanout),
.din(rdpctl_fbu_error_in),
.en(rdpctl_fbu_error_en),
// Unrecoverable error signals to RDATA: [0] => mecc_err, [1] => scb_mecc_err
assign rdpctl_fbd_unrecov_err[0] = rdpctl_crc_unrecov_err;
mcu_rdpctl_ctl_msff_ctl_macro ff_fbd_unrecov_err (
.scan_in(ff_fbd_unrecov_err_scanin),
.scan_out(ff_fbd_unrecov_err_scanout),
.din(rdpctl_fbd_unrecov_err_1_in),
.dout(rdpctl_fbd_unrecov_err[1]),
assign rdpctl_fbd_unrecov_err_1_in = fbdic_err_unrecov | fbdic_chnl_reset_error |
drif_err_state_crc_fr & rdpctl_crc_err & rdpctl_fifo_err_crc & rdpctl_fifo_scrub;
// Report CRC unrecoverable error back to FBDIC for MCU Syndrome Register
assign rdpctl_crc_unrecov_err_in = drif_err_state_crc_fr & (rdpctl_crc_error | rdpctl_crc_error_in) |
fbdic_chnl_reset_error_mode;
mcu_rdpctl_ctl_msff_ctl_macro ff_crc_unrecov_err (
.scan_in(ff_crc_unrecov_err_scanin),
.scan_out(ff_crc_unrecov_err_scanout),
.din(rdpctl_crc_unrecov_err_in),
.dout(rdpctl_crc_unrecov_err),
assign rdpctl_fbr_error_en = rdpctl_no_crc_err & rdpctl_fifo_err_crc | fbdic_err_recov | drif_err_sts_reg_ld;
assign rdpctl_fbr_error_in = rdpctl_no_crc_err & rdpctl_fifo_err_crc | fbdic_err_recov ? 1'b1 :
rdpctl_fbr_error & ~drif_ucb_data_63to54[54];
mcu_rdpctl_ctl_msff_ctl_macro__en_1 pff_err_sts_bit54 ( // FS:wmr_protect
.scan_in(pff_err_sts_bit54_wmr_scanin),
.scan_out(pff_err_sts_bit54_wmr_scanout),
.din(rdpctl_fbr_error_in),
.en(rdpctl_fbr_error_en),
// Report recoverable errors to RDATA
assign rdpctl_fbd0_recov_err_in = (rdpctl_no_crc_err & rdpctl_fifo_err_crc & ~rdpctl_fifo_l2bank | fbdic_err_recov) &
~fbdic_chnl_reset_error_mode;
assign rdpctl_fbd1_recov_err_in = rdpctl_no_crc_err & rdpctl_fifo_err_crc & rdpctl_fifo_l2bank &
~fbdic_chnl_reset_error_mode;
mcu_rdpctl_ctl_msff_ctl_macro__width_2 ff_fbd_recov_err (
.scan_in(ff_fbd_recov_err_scanin),
.scan_out(ff_fbd_recov_err_scanout),
.din({rdpctl_fbd0_recov_err_in,rdpctl_fbd1_recov_err_in}),
.dout({rdpctl_fbd0_recov_err,rdpctl_fbd1_recov_err}),
// Report CRC recoverable errors to FBDIC for MCU Syndrome Register
assign rdpctl_crc_recov_err_in = rdpctl_no_crc_err & rdpctl_fifo_err_crc & ~fbdic_chnl_reset_error_mode;
mcu_rdpctl_ctl_msff_ctl_macro ff_crc_recov_err (
.scan_in(ff_crc_recov_err_scanin),
.scan_out(ff_crc_recov_err_scanout),
.din(rdpctl_crc_recov_err_in),
.dout(rdpctl_crc_recov_err_out),
assign rdpctl_crc_recov_err = rdpctl_crc_recov_err_out | fbdic_cfgrd_crc_error;
// stage error syndrome with error signals to capture in error status register
mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_32 ff_ecc_d1 (
.scan_in(ff_ecc_d1_scanin),
.scan_out(ff_ecc_d1_scanout),
.din({readdp0_syndrome[15:0],readdp1_syndrome[15:0]}),
.dout({rdpctl0_syndrome[15:0],rdpctl1_syndrome[15:0]}),
.en(rdpctl_rddata_en[2]),
// set it only if there is no prior uncorrectable error and a new uncorrectable one happens
// OR no prior uncorrectable and no prior correctable and new correctable happens
assign rdpctl_err_sts_reg_en = (rdpctl_scrub_data_valid | rdpctl_l2t_data_valid) &
((~rdpctl_dau_error & ~rdpctl_dsu_error & (|readdp_ecc_multi_err[1:0]) & ~rdpctl_pa_err) |
(~rdpctl_dau_error & ~rdpctl_dsu_error & ~rdpctl_dac_error & ~rdpctl_dsc_error & (|readdp_ecc_single_err[1:0]))) |
assign rdpctl_err_sts_reg_in[15:0] = rdpctl_scrub_data_valid | rdpctl_l2t_data_valid & ~rdpctl_dau_error & ~rdpctl_dsu_error ?
(readdp_ecc_multi_err[0] & ~rdpctl_pa_err ? rdpctl0_syndrome[15:0] :
readdp_ecc_multi_err[1] & ~rdpctl_pa_err ? rdpctl1_syndrome[15:0] :
~rdpctl_dac_error & ~rdpctl_dsc_error & readdp_ecc_single_err[0] ? rdpctl0_syndrome[15:0] :
~rdpctl_dac_error & ~rdpctl_dsc_error & readdp_ecc_single_err[1] ? rdpctl1_syndrome[15:0] : drif_ucb_data_39to0[15:0]) :
drif_ucb_data_39to0[15:0];
mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_16 pff_err_syn ( // FS:wmr_protect
.scan_in(pff_err_syn_wmr_scanin),
.scan_out(pff_err_syn_wmr_scanout),
.din(rdpctl_err_sts_reg_in[15:0]),
.dout(rdpctl_err_sts_reg[15:0]),
.en(rdpctl_err_sts_reg_en),
//////////////////////////////////////
// DRAM ERROR RETRY REGISTER
//////////////////////////////////////
assign rdpctl_err_retry_ld_en = (rdpctl_scrub_data_valid | rdpctl_l2t_data_valid) &
((|readdp_ecc_single_err[1:0]) & ~rdpctl_dsc_error & ~rdpctl_dac_error |
(|readdp_ecc_multi_err[1:0])) & ~rdpctl_dsu_error & ~rdpctl_dau_error;
assign rdpctl_err_retry_ld_clr = rdpctl_fifo_deq_d1;
mcu_rdpctl_ctl_msff_ctl_macro__clr_1__en_1 ff_err_retry_ld (
.scan_in(ff_err_retry_ld_scanin),
.scan_out(ff_err_retry_ld_scanout),
.dout(rdpctl_err_retry_ld_out),
.en(rdpctl_err_retry_ld_en),
.clr(rdpctl_err_retry_ld_clr),
assign rdpctl_err_retry_ld = rdpctl_err_retry_ld_out | rdpctl_err_retry_ld_en;
assign rdpctl_err_retry_reg[36:0] = {rdpctl_retry_reg_valid, rdpctl_err_retry2_reg[17:0],rdpctl_err_retry1_reg[17:0]};
// Retry status for first retry read
assign rdpctl_err_retry1_reg_en = rdpctl_fifo_deq_d1 & rdpctl_fifo_err_xaction_d1 & ~rdpctl_fifo_err_xactnum_d1 &
rdpctl_fifo_err_type_d1 & ~rdpctl_retry_reg_valid | drif_err_retry_reg_ld;
assign rdpctl_err_retry1_reg_in[1:0] = rdpctl_fifo_deq_d1 & rdpctl_fifo_err_xaction_d1 & ~rdpctl_fifo_err_xactnum_d1 &
rdpctl_fifo_err_type_d1 & ~rdpctl_retry_reg_valid ?
{rdpctl_ecc_error, rdpctl_err_type & rdpctl_ecc_error | ~rdpctl_ecc_error} :
drif_ucb_data_39to0[1:0];
assign rdpctl_err_retry1_reg_in[17:2] = rdpctl_retry_syndrome[15:0];
mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_18 pff_err_retry1 ( // FS:wmr_protect
.scan_in(pff_err_retry1_wmr_scanin),
.scan_out(pff_err_retry1_wmr_scanout),
.din(rdpctl_err_retry1_reg_in[17:0]),
.dout(rdpctl_err_retry1_reg[17:0]),
.en(rdpctl_err_retry1_reg_en),
// Retry status for second retry read
assign rdpctl_err_retry2_reg_en = rdpctl_fifo_deq_d1 & rdpctl_fifo_err_xaction_d1 & rdpctl_fifo_err_xactnum_d1 &
rdpctl_fifo_err_type_d1 & ~rdpctl_retry_reg_valid | drif_err_retry_reg_ld;
assign rdpctl_err_retry2_reg_in[1:0] = rdpctl_fifo_deq_d1 & rdpctl_fifo_err_xaction_d1 & rdpctl_fifo_err_xactnum_d1 &
rdpctl_fifo_err_type_d1 & ~rdpctl_retry_reg_valid ?
{rdpctl_ecc_error, rdpctl_err_type & rdpctl_ecc_error | ~rdpctl_ecc_error} :
drif_ucb_data_39to0[19:18];
assign rdpctl_err_retry2_reg_in[17:2] = rdpctl_retry_syndrome[15:0];
mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_18 pff_err_retry2 ( // FS:wmr_protect
.scan_in(pff_err_retry2_wmr_scanin),
.scan_out(pff_err_retry2_wmr_scanout),
.din(rdpctl_err_retry2_reg_in[17:0]),
.dout(rdpctl_err_retry2_reg[17:0]),
.en(rdpctl_err_retry2_reg_en),
assign rdpctl_err_retry2_reg_en_no_ld = rdpctl_fifo_deq_d1 & rdpctl_fifo_err_xaction_d1 & rdpctl_fifo_err_xactnum_d1 &
rdpctl_fifo_err_type_d1 & ~rdpctl_retry_reg_valid;
assign rdpctl_err_retry1_reg_en_no_ld = rdpctl_fifo_deq_d1 & rdpctl_fifo_err_xaction_d1 & ~rdpctl_fifo_err_xactnum_d1 &
rdpctl_fifo_err_type_d1 & ~rdpctl_retry_reg_valid;
assign rdpctl_retry_reg_valid_in = rdpctl_retry_reg_valid & (~drif_err_retry_reg_ld | drif_ucb_data_39to0[36]) |
rdpctl_err_retry2_reg_en_no_ld |
rdpctl_err_retry1_reg_en_no_ld & (rdpctl_err_retry1_reg_in[1:0] == 2'h3) |
drif_err_retry_reg_ld & drif_ucb_data_39to0[36];
assign rdpctl_retry_reg_valid_en = 1'b1;
mcu_rdpctl_ctl_msff_ctl_macro__en_1 pff_retry_reg_valid ( // FS:wmr_protect
.scan_in(pff_retry_reg_valid_wmr_scanin),
.scan_out(pff_retry_reg_valid_wmr_scanout),
.din(rdpctl_retry_reg_valid_in),
.dout(rdpctl_retry_reg_valid),
.en(rdpctl_retry_reg_valid_en),
assign rdpctl_syndrome_dly_en = ~drif_single_channel_mode | drif_single_channel_mode & rdpctl_rddata_en[2];
mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_36 ff_syndrome_dly (
.scan_in(ff_syndrome_dly_scanin),
.scan_out(ff_syndrome_dly_scanout),
.din({rdpctl0_syndrome[15:0],rdpctl1_syndrome[15:0],readdp_ecc_single_err[1:0],readdp_ecc_multi_err[1:0]}),
.dout({rdpctl0_syndrome_d1[15:0],rdpctl1_syndrome_d1[15:0],
rdpctl_ecc_single_err_d1[1:0],rdpctl_ecc_multi_err_d1[1:0]}),
assign rdpctl_retry_syndrome[15:0] = rdpctl_ecc_multi_err_d1[0] ? rdpctl0_syndrome_d1[15:0] :
rdpctl_ecc_multi_err_d1[1] ? rdpctl1_syndrome_d1[15:0] :
readdp_ecc_multi_err[0] ? rdpctl0_syndrome[15:0] :
readdp_ecc_multi_err[1] ? rdpctl1_syndrome[15:0] :
rdpctl_ecc_single_err_d1[0] ? rdpctl0_syndrome_d1[15:0] :
rdpctl_ecc_single_err_d1[1] ? rdpctl1_syndrome_d1[15:0] :
readdp_ecc_single_err[0] ? rdpctl0_syndrome[15:0] :
//////////////////////////////////////
// DRAM ERROR ADDRESS REGISTER
//////////////////////////////////////
// This address reg can only have scrub address as load address is not kept.
assign rdpctl_err_addr_reg_en = rdpctl_scrub_data_valid & ((|readdp_ecc_multi_err[1:0]) & ~rdpctl_pa_err |
(|readdp_ecc_single_err[1:0])) & ~rdpctl_dsc_error & ~rdpctl_dsu_error | drif_err_addr_reg_ld;
assign rdpctl_err_addr_reg_in[35:0] = rdpctl_scrub_data_valid & ((|readdp_ecc_multi_err[1:0]) & ~rdpctl_pa_err |
(|readdp_ecc_single_err[1:0])) & ~rdpctl_dsc_error & ~rdpctl_dsu_error ? rdpctl_err_addr[35:0] :
drif_ucb_data_39to0[39:4];
assign rdpctl_err_addr[35:0] = rdpctl_pm_1mcu ? {2'h0, drif_scrub_addr[31:1], drif_scrub_addr[0], rdpctl_scrub_data_cnt[1:0]} :
rdpctl_pm_2mcu ? {1'b0, drif_scrub_addr[31:1], mcu_id[0], drif_scrub_addr[0], rdpctl_scrub_data_cnt[1:0]} :
{drif_scrub_addr[31:1], mcu_id[1:0], drif_scrub_addr[0], rdpctl_scrub_data_cnt[1:0]};
mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_36 pff_err_addr_reg ( // FS:wmr_protect
.scan_in(pff_err_addr_reg_wmr_scanin),
.scan_out(pff_err_addr_reg_wmr_scanout),
.din(rdpctl_err_addr_reg_in[35:0]),
.dout(rdpctl_err_addr_reg[35:0]),
.en(rdpctl_err_addr_reg_en),
assign rdpctl_scrub_data_cnt[0] = readdp_ecc_multi_err[0] | readdp_ecc_single_err[0] & ~readdp_ecc_multi_err[1];
assign rdpctl_scrub_data_cnt_in[1] = ~rdpctl_scrub_data_cnt[1];
assign rdpctl_scrub_data_cnt_en = rdpctl_scrub_data_valid;
mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_1 ff_scrub_data_cnt (
.scan_in(ff_scrub_data_cnt_scanin),
.scan_out(ff_scrub_data_cnt_scanout),
.din(rdpctl_scrub_data_cnt_in[1]),
.dout(rdpctl_scrub_data_cnt[1]),
.en(rdpctl_scrub_data_cnt_en),
////////////////////////////////////////
// SECC ERROR COUNTER - for generating interrupts and debug triggers to NCU
////////////////////////////////////////
assign rdpctl_err_cnt[15:0] = rdpctl_secc_cnt[15:0];
assign rdpctl_secc_int_en = drif_err_cnt_reg_ld | rdpctl_secc_cnt_intr_in;
assign rdpctl_secc_int_in = rdpctl_secc_cnt_intr_in ? 1'b0 : (|drif_ucb_data_39to0[15:0]);
mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_1 pff_secc_int_en ( // FS:wmr_protect
.scan_in(pff_secc_int_en_wmr_scanin),
.scan_out(pff_secc_int_en_wmr_scanout),
.din(rdpctl_secc_int_in),
.dout(rdpctl_secc_int_enabled),
assign rdpctl_secc_cnt_en = drif_err_cnt_reg_ld | (|readdp_ecc_single_err[1:0]) & rdpctl_secc_int_enabled &
(rdpctl_scrub_data_valid | rdpctl_l2t_data_valid);
assign rdpctl_secc_cnt_next[15:0] = (rdpctl_secc_cnt[15:0] == 16'h0) ? 16'h0 : rdpctl_secc_cnt[15:0] - 16'h1;
assign rdpctl_secc_cnt_in[15:0] = (|readdp_ecc_single_err[1:0]) & rdpctl_secc_int_enabled & (rdpctl_scrub_data_valid | rdpctl_l2t_data_valid) ?
rdpctl_secc_cnt_next[15:0] : drif_ucb_data_39to0[15:0];
mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_16 pff_secc_cnt ( // FS:wmr_protect
.scan_in(pff_secc_cnt_wmr_scanin),
.scan_out(pff_secc_cnt_wmr_scanout),
.din(rdpctl_secc_cnt_in[15:0]),
.dout(rdpctl_secc_cnt[15:0]),
assign rdpctl_secc_cnt_intr_in = rdpctl_secc_int_enabled & ~(|rdpctl_secc_cnt[15:0]);
mcu_rdpctl_ctl_msff_ctl_macro ff_secc_cnt_intr (
.scan_in(ff_secc_cnt_intr_scanin),
.scan_out(ff_secc_cnt_intr_scanout),
.din(rdpctl_secc_cnt_intr_in),
.dout(rdpctl_secc_cnt_intr),
////////////////////////////////////////
// SECC DEBUG TRIGGER ENABLE REGISTER
////////////////////////////////////////
assign rdpctl_dbg_trig_enable_in[5:1] = drif_ucb_data_39to0[5:1];
mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_5 pff_dbg_trig ( // FS:wmr_protect
.scan_in(pff_dbg_trig_wmr_scanin),
.scan_out(pff_dbg_trig_wmr_scanout),
.din(rdpctl_dbg_trig_enable_in[5:1]),
.dout({rdpctl_dtm_atspeed, rdpctl_dtm_mask_chnl[1:0], rdpctl_dbg_trig_enable, rdpctl_mask_err}),
.en(drif_dbg_trig_reg_ld),
assign rdpctl_dtm_chnl_enable[1:0] = {2{fbdic_serdes_dtm}} & (~rdpctl_dtm_mask_chnl[1:0]);
////////////////////////////////////////
// The interpretation of the parity is as following ecc[15:0] = {p0,p1,p2,p3} where p3 is not used
// The error location is as = {err_in_p3, err_in_p2, ... err_in_d2, err_in_d1, err_in_d0}
// If the error location bit is 1, and to create mask in failover mode set all the bits left of 1 to 1
// (including the bit 1 set in err location) upto bit location 34.
// Also this error location once logged will not be over written when another error occurs till S/W
// resets the appropriate bit in the error status register.
////////////////////////////////////////
assign rdpctl_secc_loc_en = (|readdp_ecc_single_err[1:0]) & (rdpctl_scrub_data_valid & ~rdpctl_dsc_error |
rdpctl_l2t_data_valid & ~rdpctl_dac_error) |
assign rdpctl_err_loc_in[35:0] = readdp_ecc_single_err[1] & (rdpctl_scrub_data_valid & ~rdpctl_dsc_error |
rdpctl_l2t_data_valid & ~rdpctl_dac_error) ? rdpctl1_ecc_loc[35:0] :
readdp_ecc_single_err[0] & (rdpctl_scrub_data_valid & ~rdpctl_dsc_error |
rdpctl_l2t_data_valid & ~rdpctl_dac_error) ? rdpctl0_ecc_loc[35:0] : drif_ucb_data_39to0[35:0];
mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_36 pff_err_loc ( // FS:wmr_protect
.scan_in(pff_err_loc_wmr_scanin),
.scan_out(pff_err_loc_wmr_scanout),
.din(rdpctl_err_loc_in[35:0]),
.dout(rdpctl_err_loc[35:0]),
////////////////////////////////////////
// Scrub valid signals to rdata
////////////////////////////////////////
assign rdpctl_scrb0_err_valid_in = rdpctl_mcu_data_valid & rdpctl_fifo_scrub & ~drif_scrub_addr[0] & ~rdpctl_fifo_err_xaction &
(~rdpctl_crc_error_in & ~rdpctl_crc_error | drif_err_state_crc_fr);
assign rdpctl_scrb1_err_valid_in = rdpctl_mcu_data_valid & rdpctl_fifo_scrub & drif_scrub_addr[0] & ~rdpctl_fifo_err_xaction &
(~rdpctl_crc_error_in & ~rdpctl_crc_error | drif_err_state_crc_fr);
mcu_rdpctl_ctl_msff_ctl_macro__width_2 ff_scrub_ecc_err (
.scan_in(ff_scrub_ecc_err_scanin),
.scan_out(ff_scrub_ecc_err_scanout),
.din({rdpctl_scrb0_err_valid_in,rdpctl_scrb1_err_valid_in}),
.dout({rdpctl_scrb0_err_valid,rdpctl_scrb1_err_valid}),
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
mcu_rdpctl_ctl_msff_ctl_macro__clr_1__en_1__width_1 ff_rd_dummy_req0 (
.scan_in(ff_rd_dummy_req0_scanin),
.scan_out(ff_rd_dummy_req0_scanout),
.dout(rdpctl0_rd_dummy_req),
.en(rdpctl0_rd_dummy_req_en),
.clr(rdpctl0_dummy_data_valid),
mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_5 ff_rd_dummy0 (
.scan_in(ff_rd_dummy0_scanin),
.scan_out(ff_rd_dummy0_scanout),
.din({rdpctl0_rd_dummy_req_addr5_in, rdpctl0_rd_dummy_req_id_in[2:0], rdpctl0_rd_dummy_addr_err_in}),
.dout({rdpctl0_rd_dummy_req_addr5, rdpctl0_rd_dummy_req_id[2:0], rdpctl0_rd_dummy_addr_err}),
.en(rdpctl0_rd_dummy_req_en),
mcu_rdpctl_ctl_msff_ctl_macro__clr_1__en_1__width_1 ff_rd_dummy_req1 (
.scan_in(ff_rd_dummy_req1_scanin),
.scan_out(ff_rd_dummy_req1_scanout),
.dout(rdpctl1_rd_dummy_req),
.en(rdpctl1_rd_dummy_req_en),
.clr(rdpctl1_dummy_data_valid),
mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_5 ff_rd_dummy1 (
.scan_in(ff_rd_dummy1_scanin),
.scan_out(ff_rd_dummy1_scanout),
.din({rdpctl1_rd_dummy_req_addr5_in, rdpctl1_rd_dummy_req_id_in[2:0], rdpctl1_rd_dummy_addr_err_in}),
.dout({rdpctl1_rd_dummy_req_addr5, rdpctl1_rd_dummy_req_id[2:0], rdpctl1_rd_dummy_addr_err}),
.en(rdpctl1_rd_dummy_req_en),
// give priority to first dummy requester
// only want one valid at a time in case one has a pa_err
assign rdpctl_dummy_priority_in = rdpctl1_rd_dummy_req & ~rdpctl0_rd_dummy_req ? 1'b1 :
rdpctl0_rd_dummy_req & ~rdpctl1_rd_dummy_req ? 1'b0 :
mcu_rdpctl_ctl_msff_ctl_macro ff_dummy_priority (
.scan_in(ff_dummy_priority_scanin),
.scan_out(ff_dummy_priority_scanout),
.din(rdpctl_dummy_priority_in),
.dout(rdpctl_dummy_priority),
assign rdpctl0_dummy_data_valid_in = (~fbdic_rddata_vld & ~rdpctl_mcu_data_valid |
fbdic_rddata_vld & ~rdpctl_mcu_data_valid & rdpctl0_dummy_data_valid) &
rdpctl0_rd_dummy_req & (~rdpctl_dummy_priority | ~rdpctl1_rd_dummy_req);
assign rdpctl1_dummy_data_valid_in = (~fbdic_rddata_vld & ~rdpctl_mcu_data_valid |
fbdic_rddata_vld & ~rdpctl_mcu_data_valid & rdpctl1_dummy_data_valid) &
rdpctl1_rd_dummy_req & (rdpctl_dummy_priority | ~rdpctl0_rd_dummy_req);
mcu_rdpctl_ctl_msff_ctl_macro__width_2 ff_dummy_data_valid (
.scan_in(ff_dummy_data_valid_scanin),
.scan_out(ff_dummy_data_valid_scanout),
.din({rdpctl0_dummy_data_valid_in,rdpctl1_dummy_data_valid_in}),
.dout({rdpctl0_dummy_data_valid,rdpctl1_dummy_data_valid}),
// Write enable for scrub data buffer, for data from 1st error retry
assign rdpctl_scrub_wren = drif_single_channel_mode ? rdpctl_scrub_wren_out :
rdpctl_fifo_err_xaction & ~rdpctl_fifo_err_xactnum & rdpctl_mcu_data_valid;
assign rdpctl_scrub_wren_in = rdpctl_fifo_err_xaction & ~rdpctl_fifo_err_xactnum &
fbdic_rddata_vld & rdpctl_rddata_state[0];
mcu_rdpctl_ctl_msff_ctl_macro ff_scrub_wren (
.scan_in(ff_scrub_wren_scanin),
.scan_out(ff_scrub_wren_scanout),
.din(rdpctl_scrub_wren_in),
.dout(rdpctl_scrub_wren_out),
// Mux controls for single-DIMM mode
assign rdpctl_rddata_en[1:0] = drif_single_channel_mode ?
{rdpctl_rddata_state[0] | ~fbdic_rddata_vld, ~rdpctl_rddata_state[0] | ~fbdic_rddata_vld} : 2'h3;
assign rdpctl_rddata_en[2] = drif_single_channel_mode ? ~rdpctl_rddata_state[0] : 1'b1;
assign rdpctl_rddata_state_in[1:0] = drif_single_channel_mode ? rdpctl_rddata_state[1:0] + 2'h1 :
{1'b0, ~rdpctl_rddata_state[0]};
mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_2 ff_rddata_state (
.scan_in(ff_rddata_state_scanin),
.scan_out(ff_rddata_state_scanout),
.din(rdpctl_rddata_state_in[1:0]),
.dout(rdpctl_rddata_state[1:0]),
assign rdpctl_rddata_vld = drif_single_channel_mode ? fbdic_rddata_vld & rdpctl_rddata_state[1] : fbdic_rddata_vld;
// address parity for readdp block
assign rdpctl_radr_parity = fbdic_rddata_vld & (rdpctl_fifo_deq ? rdpctl_fifo_addr_parity_p1 : rdpctl_fifo_addr_parity);
// ECC Error injection from NCU
mcu_rdpctl_ctl_msff_ctl_macro ff_err_ecci (
.scan_in(ff_err_ecci_scanin),
.scan_out(ff_err_ecci_scanout),
assign rdpctl_inj_ecc_err = rdpctl_err_ecci & ~rdpctl_rddata_state[0] & fbdic_rddata_vld;
mcu_rdpctl_ctl_spare_ctl_macro__num_6 spares (
.scan_out(spares_scanout),
assign ff_pm_mcus_scanin = scan_in ;
assign ff_dummy_req0_scanin = ff_pm_mcus_scanout ;
assign ff_dummy_req1_scanin = ff_dummy_req0_scanout ;
assign ff_ddp_data_valid_scanin = ff_dummy_req1_scanout ;
assign ff_ecc_loc_scanin = ff_ddp_data_valid_scanout;
assign ff_data_cnt_scanin = ff_ecc_loc_scanout ;
assign otq_scanin = ff_data_cnt_scanout ;
assign ff_drif_clear_ent_scanin = otq_scanout ;
assign ff_l2t_data_valid_scanin = ff_drif_clear_ent_scanout;
assign ff_scrub_data_valid_scanin = ff_l2t_data_valid_scanout;
assign ff_qword_id_scanin = ff_scrub_data_valid_scanout;
assign ff_rd_req_id_scanin = ff_qword_id_scanout ;
assign ff_pa_err_scanin = ff_rd_req_id_scanout ;
assign ff_crc_err_dly_scanin = ff_pa_err_scanout ;
assign ff_mecc_errors_scanin = ff_crc_err_dly_scanout ;
assign ff_err_fifo_data_scanin = ff_mecc_errors_scanout ;
assign ff_fifo_deq_d1_scanin = ff_err_fifo_data_scanout ;
assign ff_fbd_unrecov_err_scanin = ff_fifo_deq_d1_scanout ;
assign ff_crc_unrecov_err_scanin = ff_fbd_unrecov_err_scanout;
assign ff_fbd_recov_err_scanin = ff_crc_unrecov_err_scanout;
assign ff_crc_recov_err_scanin = ff_fbd_recov_err_scanout ;
assign ff_ecc_d1_scanin = ff_crc_recov_err_scanout ;
assign ff_err_retry_ld_scanin = ff_ecc_d1_scanout ;
assign ff_syndrome_dly_scanin = ff_err_retry_ld_scanout ;
assign ff_scrub_data_cnt_scanin = ff_syndrome_dly_scanout ;
assign ff_secc_cnt_intr_scanin = ff_scrub_data_cnt_scanout;
assign ff_scrub_ecc_err_scanin = ff_secc_cnt_intr_scanout ;
assign ff_rd_dummy_req0_scanin = ff_scrub_ecc_err_scanout ;
assign ff_rd_dummy0_scanin = ff_rd_dummy_req0_scanout ;
assign ff_rd_dummy_req1_scanin = ff_rd_dummy0_scanout ;
assign ff_rd_dummy1_scanin = ff_rd_dummy_req1_scanout ;
assign ff_dummy_priority_scanin = ff_rd_dummy1_scanout ;
assign ff_dummy_data_valid_scanin = ff_dummy_priority_scanout;
assign ff_scrub_wren_scanin = ff_dummy_data_valid_scanout;
assign ff_rddata_state_scanin = ff_scrub_wren_scanout ;
assign ff_err_ecci_scanin = ff_rddata_state_scanout ;
assign spares_scanin = ff_err_ecci_scanout ;
assign scan_out = spares_scanout ;
assign pff_err_sts_bit63_wmr_scanin = wmr_scan_in ;
assign pff_err_sts_bit62_wmr_scanin = pff_err_sts_bit63_wmr_scanout;
assign pff_err_sts_bit61_wmr_scanin = pff_err_sts_bit62_wmr_scanout;
assign pff_err_sts_bit60_wmr_scanin = pff_err_sts_bit61_wmr_scanout;
assign pff_err_sts_bit59_wmr_scanin = pff_err_sts_bit60_wmr_scanout;
assign pff_err_sts_bit58_wmr_scanin = pff_err_sts_bit59_wmr_scanout;
assign pff_err_sts_bit57_wmr_scanin = pff_err_sts_bit58_wmr_scanout;
assign pff_err_sts_bit56_wmr_scanin = pff_err_sts_bit57_wmr_scanout;
assign pff_err_sts_bit55_wmr_scanin = pff_err_sts_bit56_wmr_scanout;
assign pff_err_sts_bit54_wmr_scanin = pff_err_sts_bit55_wmr_scanout;
assign pff_err_syn_wmr_scanin = pff_err_sts_bit54_wmr_scanout;
assign pff_err_retry1_wmr_scanin = pff_err_syn_wmr_scanout ;
assign pff_err_retry2_wmr_scanin = pff_err_retry1_wmr_scanout;
assign pff_retry_reg_valid_wmr_scanin = pff_err_retry2_wmr_scanout;
assign pff_err_addr_reg_wmr_scanin = pff_retry_reg_valid_wmr_scanout;
assign pff_secc_int_en_wmr_scanin = pff_err_addr_reg_wmr_scanout;
assign pff_secc_cnt_wmr_scanin = pff_secc_int_en_wmr_scanout;
assign pff_dbg_trig_wmr_scanin = pff_secc_cnt_wmr_scanout ;
assign pff_err_loc_wmr_scanin = pff_dbg_trig_wmr_scanout ;
assign wmr_scan_out = pff_err_loc_wmr_scanout ;
// any PARAMS parms go into naming of macro
module mcu_rdpctl_ctl_l1clkhdr_ctl_macro (
// any PARAMS parms go into naming of macro
module mcu_rdpctl_ctl_msff_ctl_macro__width_2 (
assign fdin[1:0] = din[1:0];
// any PARAMS parms go into naming of macro
module mcu_rdpctl_ctl_msff_ctl_macro__width_6 (
assign fdin[5:0] = din[5:0];
// any PARAMS parms go into naming of macro
module mcu_rdpctl_ctl_msff_ctl_macro (
assign fdin[0:0] = din[0:0];
// any PARAMS parms go into naming of macro
module mcu_rdpctl_ctl_msff_ctl_macro__width_72 (
assign fdin[71:0] = din[71:0];
.so({so[70:0],scan_out}),
// any PARAMS parms go into naming of macro
module mcu_rdpctl_ctl_msff_ctl_macro__width_1 (
assign fdin[0:0] = din[0:0];
// any PARAMS parms go into naming of macro
module mcu_rdpctl_ctl_msff_ctl_macro__width_5 (
assign fdin[4:0] = din[4:0];
// any PARAMS parms go into naming of macro
module mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_20 (
assign fdin[19:0] = (din[19:0] & {20{en}}) | (dout[19:0] & ~{20{en}});
.so({so[18:0],scan_out}),
// any PARAMS parms go into naming of macro
module mcu_rdpctl_ctl_msff_ctl_macro__width_16 (
assign fdin[15:0] = din[15:0];
.so({so[14:0],scan_out}),
// any PARAMS parms go into naming of macro
module mcu_rdpctl_ctl_msff_ctl_macro__width_3 (
assign fdin[2:0] = din[2:0];
// any PARAMS parms go into naming of macro
module mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_14 (
assign fdin[13:0] = (din[13:0] & {14{en}}) | (dout[13:0] & ~{14{en}});
.so({so[12:0],scan_out}),
// any PARAMS parms go into naming of macro
module mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_1 (
assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}});
// any PARAMS parms go into naming of macro
module mcu_rdpctl_ctl_msff_ctl_macro__en_1 (
assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}});
// any PARAMS parms go into naming of macro
module mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_32 (
assign fdin[31:0] = (din[31:0] & {32{en}}) | (dout[31:0] & ~{32{en}});
.so({so[30:0],scan_out}),
// any PARAMS parms go into naming of macro
module mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_16 (
assign fdin[15:0] = (din[15:0] & {16{en}}) | (dout[15:0] & ~{16{en}});
.so({so[14:0],scan_out}),
// any PARAMS parms go into naming of macro
module mcu_rdpctl_ctl_msff_ctl_macro__clr_1__en_1 (
assign fdin[0:0] = (din[0:0] & {1{en}} & ~{1{clr}}) | (dout[0:0] & ~{1{en}} & ~{1{clr}});
// any PARAMS parms go into naming of macro
module mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_18 (
assign fdin[17:0] = (din[17:0] & {18{en}}) | (dout[17:0] & ~{18{en}});
.so({so[16:0],scan_out}),
// any PARAMS parms go into naming of macro
module mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_36 (
assign fdin[35:0] = (din[35:0] & {36{en}}) | (dout[35:0] & ~{36{en}});
.so({so[34:0],scan_out}),
// any PARAMS parms go into naming of macro
module mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_5 (
assign fdin[4:0] = (din[4:0] & {5{en}}) | (dout[4:0] & ~{5{en}});
// any PARAMS parms go into naming of macro
module mcu_rdpctl_ctl_msff_ctl_macro__clr_1__en_1__width_1 (
assign fdin[0:0] = (din[0:0] & {1{en}} & ~{1{clr}}) | (dout[0:0] & ~{1{en}} & ~{1{clr}});
// any PARAMS parms go into naming of macro
module mcu_rdpctl_ctl_msff_ctl_macro__en_1__width_2 (
assign fdin[1:0] = (din[1:0] & {2{en}}) | (dout[1:0] & ~{2{en}});
// Description: Spare gate macro for control blocks
// Param num controls the number of times the macro is added
// flops=0 can be used to use only combination spare logic
module mcu_rdpctl_ctl_spare_ctl_macro__num_6 (
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;
wire spare3_buf_32x_unused;
wire spare3_nand3_8x_unused;
wire spare3_inv_8x_unused;
wire spare3_aoi22_4x_unused;
wire spare3_buf_8x_unused;
wire spare3_oai22_4x_unused;
wire spare3_inv_16x_unused;
wire spare3_nand2_16x_unused;
wire spare3_nor3_4x_unused;
wire spare3_nand2_8x_unused;
wire spare3_buf_16x_unused;
wire spare3_nor2_16x_unused;
wire spare3_inv_32x_unused;
wire spare4_buf_32x_unused;
wire spare4_nand3_8x_unused;
wire spare4_inv_8x_unused;
wire spare4_aoi22_4x_unused;
wire spare4_buf_8x_unused;
wire spare4_oai22_4x_unused;
wire spare4_inv_16x_unused;
wire spare4_nand2_16x_unused;
wire spare4_nor3_4x_unused;
wire spare4_nand2_8x_unused;
wire spare4_buf_16x_unused;
wire spare4_nor2_16x_unused;
wire spare4_inv_32x_unused;
wire spare5_buf_32x_unused;
wire spare5_nand3_8x_unused;
wire spare5_inv_8x_unused;
wire spare5_aoi22_4x_unused;
wire spare5_buf_8x_unused;
wire spare5_oai22_4x_unused;
wire spare5_inv_16x_unused;
wire spare5_nand2_16x_unused;
wire spare5_nor3_4x_unused;
wire spare5_nand2_8x_unused;
wire spare5_buf_16x_unused;
wire spare5_nor2_16x_unused;
wire spare5_inv_32x_unused;
cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
cl_u1_buf_32x spare0_buf_32x (.in(1'b1),
.out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
.out(spare0_nand3_8x_unused));
cl_u1_inv_8x spare0_inv_8x (.in(1'b1),
.out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
.out(spare0_aoi22_4x_unused));
cl_u1_buf_8x spare0_buf_8x (.in(1'b1),
.out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
.out(spare0_oai22_4x_unused));
cl_u1_inv_16x spare0_inv_16x (.in(1'b1),
.out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
.out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
.out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
.out(spare0_nand2_8x_unused));
cl_u1_buf_16x spare0_buf_16x (.in(1'b1),
.out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
.out(spare0_nor2_16x_unused));
cl_u1_inv_32x spare0_inv_32x (.in(1'b1),
.out(spare0_inv_32x_unused));
cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
cl_u1_buf_32x spare1_buf_32x (.in(1'b1),
.out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
.out(spare1_nand3_8x_unused));
cl_u1_inv_8x spare1_inv_8x (.in(1'b1),
.out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
.out(spare1_aoi22_4x_unused));
cl_u1_buf_8x spare1_buf_8x (.in(1'b1),
.out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
.out(spare1_oai22_4x_unused));
cl_u1_inv_16x spare1_inv_16x (.in(1'b1),
.out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
.out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
.out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
.out(spare1_nand2_8x_unused));
cl_u1_buf_16x spare1_buf_16x (.in(1'b1),
.out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
.out(spare1_nor2_16x_unused));
cl_u1_inv_32x spare1_inv_32x (.in(1'b1),
.out(spare1_inv_32x_unused));
cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
cl_u1_buf_32x spare2_buf_32x (.in(1'b1),
.out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
.out(spare2_nand3_8x_unused));
cl_u1_inv_8x spare2_inv_8x (.in(1'b1),
.out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
.out(spare2_aoi22_4x_unused));
cl_u1_buf_8x spare2_buf_8x (.in(1'b1),
.out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
.out(spare2_oai22_4x_unused));
cl_u1_inv_16x spare2_inv_16x (.in(1'b1),
.out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
.out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
.out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
.out(spare2_nand2_8x_unused));
cl_u1_buf_16x spare2_buf_16x (.in(1'b1),
.out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
.out(spare2_nor2_16x_unused));
cl_u1_inv_32x spare2_inv_32x (.in(1'b1),
.out(spare2_inv_32x_unused));
cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
cl_u1_buf_32x spare3_buf_32x (.in(1'b1),
.out(spare3_buf_32x_unused));
cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
.out(spare3_nand3_8x_unused));
cl_u1_inv_8x spare3_inv_8x (.in(1'b1),
.out(spare3_inv_8x_unused));
cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
.out(spare3_aoi22_4x_unused));
cl_u1_buf_8x spare3_buf_8x (.in(1'b1),
.out(spare3_buf_8x_unused));
cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
.out(spare3_oai22_4x_unused));
cl_u1_inv_16x spare3_inv_16x (.in(1'b1),
.out(spare3_inv_16x_unused));
cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
.out(spare3_nand2_16x_unused));
cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
.out(spare3_nor3_4x_unused));
cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
.out(spare3_nand2_8x_unused));
cl_u1_buf_16x spare3_buf_16x (.in(1'b1),
.out(spare3_buf_16x_unused));
cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
.out(spare3_nor2_16x_unused));
cl_u1_inv_32x spare3_inv_32x (.in(1'b1),
.out(spare3_inv_32x_unused));
cl_sc1_msff_8x spare4_flop (.l1clk(l1clk),
cl_u1_buf_32x spare4_buf_32x (.in(1'b1),
.out(spare4_buf_32x_unused));
cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1),
.out(spare4_nand3_8x_unused));
cl_u1_inv_8x spare4_inv_8x (.in(1'b1),
.out(spare4_inv_8x_unused));
cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1),
.out(spare4_aoi22_4x_unused));
cl_u1_buf_8x spare4_buf_8x (.in(1'b1),
.out(spare4_buf_8x_unused));
cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1),
.out(spare4_oai22_4x_unused));
cl_u1_inv_16x spare4_inv_16x (.in(1'b1),
.out(spare4_inv_16x_unused));
cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1),
.out(spare4_nand2_16x_unused));
cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0),
.out(spare4_nor3_4x_unused));
cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1),
.out(spare4_nand2_8x_unused));
cl_u1_buf_16x spare4_buf_16x (.in(1'b1),
.out(spare4_buf_16x_unused));
cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0),
.out(spare4_nor2_16x_unused));
cl_u1_inv_32x spare4_inv_32x (.in(1'b1),
.out(spare4_inv_32x_unused));
cl_sc1_msff_8x spare5_flop (.l1clk(l1clk),
cl_u1_buf_32x spare5_buf_32x (.in(1'b1),
.out(spare5_buf_32x_unused));
cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1),
.out(spare5_nand3_8x_unused));
cl_u1_inv_8x spare5_inv_8x (.in(1'b1),
.out(spare5_inv_8x_unused));
cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1),
.out(spare5_aoi22_4x_unused));
cl_u1_buf_8x spare5_buf_8x (.in(1'b1),
.out(spare5_buf_8x_unused));
cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1),
.out(spare5_oai22_4x_unused));
cl_u1_inv_16x spare5_inv_16x (.in(1'b1),
.out(spare5_inv_16x_unused));
cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1),
.out(spare5_nand2_16x_unused));
cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0),
.out(spare5_nor3_4x_unused));
cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1),
.out(spare5_nand2_8x_unused));
cl_u1_buf_16x spare5_buf_16x (.in(1'b1),
.out(spare5_buf_16x_unused));
cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0),
.out(spare5_nor2_16x_unused));
cl_u1_inv_32x spare5_inv_32x (.in(1'b1),
.out(spare5_inv_32x_unused));
projects / OpenSPARC-T2-DV / blob