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// OpenSPARC T2 Processor File: fflp_fcram_arb.v
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/**********************************************************************/
/*module name: fflp_fcram_arb */
/*description: Aabitration between CPU access and flow */
/*child modules in: none */
/*author name: Jeanne Cai */
/*date created: 16-03-2004 */
/* Copyright (c) 2004, Sun Microsystems, Inc. */
/* Sun Proprietary and Confidential */
/**********************************************************************/
input[3:0] fcram_lookup_ratio;
input fwd_no_fc_sched_sm;
input cpu_fcram_req_sync;
wire[3:0] fwd_sched_cnt_in;
wire cpu_fcram_req_sync_d;
always @ (state or fc_lookup_req or is_cpu_req or
srch_burst_done or cpu_burst_done_sm or
do_cpu_cycle or fwd_reqs_served)
case (state) //synopsys parallel_case full_case
// 0in < case -full -parallel -message "0in ERROR: case check in fflp_fcram_arb:state"
if (do_cpu_cycle & !cpu_burst_done_sm)
if (srch_burst_done & fwd_reqs_served)
else if (srch_burst_done)
default: next_state = FWD_ARB;
assign fwd_sched_in = fwd_fc_sched_sm | fwd_no_fc_sched_sm;
dffr #(2) state_reg (cclk, reset, next_state, state);
dffr #(1) fwd_sched_reg (cclk, reset, fwd_sched_in, fwd_sched);
dffr #(1) fwd_fc_sched_reg (cclk, reset, fwd_fc_sched_sm, fwd_fc_sched);
dffr #(1) cpu_sched_reg (cclk, reset, cpu_sched_sm, cpu_sched);
dffr #(1) fwd_sched_1_reg (cclk, reset, fwd_sched, fwd_sched_1);
dffr #(1) fwd_sched_2_reg (cclk, reset, fwd_sched_1, fwd_sched_2);
dffr #(1) fc_fifo_ren_reg (cclk, reset, fc_fifo_ren_in, fc_fifo_ren);
assign fc_fifo_ren_in = fwd_sched | fwd_sched_1 | fwd_sched_2;
/*********************************************************************/
//allocate load balance, cpu bandwidth
/*********************************************************************/
assign fwd_reqs_served = (fwd_sched_cnt == fcram_lookup_ratio);
assign fwd_sched_cnt_en = fwd_fc_sched_sm | cpu_sched_sm;
assign fwd_sched_cnt_in = (cpu_sched_sm | fwd_reqs_served & fwd_fc_sched_sm) ? 4'b0000 : (fwd_sched_cnt + 4'd1);
dffre #(4) fwd_sched_cnt_reg (cclk, reset, fwd_sched_cnt_en, fwd_sched_cnt_in, fwd_sched_cnt);
assign cpu_req_pulse = cpu_fcram_req_sync & !cpu_fcram_req_sync_d;
assign is_cpu_req_en = cpu_req_pulse | cpu_sched;
assign is_cpu_req_in = cpu_req_pulse ? 1'b1 : 1'b0;
dffr #(1) cpu_req_dly_reg (cclk, reset, cpu_fcram_req_sync, cpu_fcram_req_sync_d);
dffre #(1) is_cpu_req_reg (cclk, reset, is_cpu_req_en, is_cpu_req_in, is_cpu_req);
assign do_srch_cycle_en = fwd_fc_sched | srch_burst_done;
assign do_srch_cycle_in = fwd_fc_sched ? 1'b1 : 1'b0;
assign do_cpu_cycle_en = cpu_sched | cpu_burst_done_sm;
assign do_cpu_cycle_in = cpu_sched ? 1'b1 : 1'b0;
dffre #(1) do_srch_cycle_reg (cclk, reset, do_srch_cycle_en, do_srch_cycle_in, do_srch_cycle);
dffre #(1) do_cpu_cycle_reg (cclk, reset, do_cpu_cycle_en, do_cpu_cycle_in, do_cpu_cycle);