design/sys/iop/niu/rtl/niu_smx_regfl.v

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//
// OpenSPARC T2 Processor File: niu_smx_regfl.v
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module niu_smx_regfl(
  clk,
  reset_l,
  wr,
  addr_wr,
  data_wr,
  rd,
  addr_rd,
  data_rd
);

// synopsys template

  parameter DATA_WIDTH= 100;
  parameter ADDR_WIDTH= 5;
  parameter ENTRY_SIZE= 1<<ADDR_WIDTH;
  input reset_l;
  input clk;
  input wr;
  input [ADDR_WIDTH-1:0] addr_wr;
  input [ADDR_WIDTH-1:0] addr_rd;
  input rd;
  input [DATA_WIDTH-1:0] data_wr;
  output [DATA_WIDTH-1:0] data_rd;

  reg [DATA_WIDTH-1:0] data_rd;
  reg [DATA_WIDTH-1:0] data[0:ENTRY_SIZE-1];
  integer i;

  always @(posedge clk) begin
    if(!reset_l) begin
      for(i=0; i<ENTRY_SIZE; i=i+1)
        data[i]<= `SMX_PD  {DATA_WIDTH{1'b0}};
    end
    else begin
      if(wr)begin
        data[addr_wr]<= `SMX_PD  data_wr;
      end
    end
  end

  always @(posedge clk) begin
    if(rd) begin
      data_rd<= `SMX_PD  data[addr_rd];
    end
  end

endmodule


/*
// not use; to be removed
module niu_smx_regfl_nfo( // non flop out
  clk,
  reset_l,
  wr,
  addr_wr,
  data_wr,
  addr_rd,
  data_rd
);


  parameter DATA_WIDTH= 100;
  parameter ADDR_WIDTH= 5;
  parameter ENTRY_SIZE= 1<<ADDR_WIDTH;
  input reset_l;
  input clk;
  input wr;
  input [ADDR_WIDTH-1:0] addr_wr;
  input [ADDR_WIDTH-1:0] addr_rd;
  input [DATA_WIDTH-1:0] data_wr;
  output [DATA_WIDTH-1:0] data_rd;

  reg [DATA_WIDTH-1:0] data[0:ENTRY_SIZE-1];
  integer i;

  always @(posedge clk) begin
    if(!reset_l) begin
      for(i=0; i<ENTRY_SIZE; i=i+1)
        data[i]<= `SMX_PD  {DATA_WIDTH{1'b0}};
    end
    else begin
      if(wr)begin
        data[addr_wr]<= `SMX_PD  data_wr;
      end
    end
  end

  wire [DATA_WIDTH-1:0] data_rd_n= data[addr_rd];
  wire [DATA_WIDTH-1:0] data_rd= data_rd_n;

endmodule
*/