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// OpenSPARC T2 Processor File: niu_smx_sm_req_siiarb.v
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module niu_smx_sm_req_siiarb(
wreq_cmdff_rd, wreq_pcmd_ff_rd, rdreq_cmdff_rd, xmitflag, rwflag,
hdr_data, bypass, o_enq, b_enq, arb_cs,
clk, reset_l, wreq_cmdff_rdata, wreq_cmdff_empty,
wreq_pcmd_ff_rdata, wreq_pcmd_ff_empty, rdreq_cmdff_rdata,
rdreq_cmdff_empty, nxt_xmit, ocr_avail, bcr_avail,
input [65:0] wreq_cmdff_rdata;
input wreq_cmdff_empty; // not use
input [3:0] wreq_pcmd_ff_rdata;
input wreq_pcmd_ff_empty; // use this as wr req empty status
input [65:0] rdreq_cmdff_rdata;
output rwflag; // 0= rd, 1= wr
output [128:0] hdr_data; // added 121405 [128] to invalidate rdreq
input [63:0] tid_valid_rdata_bus;
// wire [15:0] hdr_tag= rdreq_cmdff_rdata[`SMX_CMDFF_POS_ID];
// extract exact field to avoid vlint bus_notused warning
wire [5:0] hdr_tid= rdreq_cmdff_rdata[56:51];
wire tag_is_valid_n= tid_valid_rdata_bus[hdr_tid];
wire rd_cmd_order= rdreq_cmdff_rdata[`SMX_CMDFF_POS_ORDER];
wire rcmd_is_order_n= (rd_cmd_order==`SMX_CMD_ORDER);
wire rcmd_is_bypass_n= (rd_cmd_order==`SMX_CMD_BYPASS);
wire rd_cr_avail_n= (rcmd_is_order_n & ocr_avail) |
(rcmd_is_bypass_n & bcr_avail);
wire rd_rdy_n= ~rdreq_cmdff_empty & rd_cr_avail_n;
wire wr_cmd_order= wreq_cmdff_rdata[`SMX_CMDFF_POS_ORDER];
wire wcmd_is_order_n= (wr_cmd_order==`SMX_CMD_ORDER);
wire wcmd_is_bypass_n= (wr_cmd_order==`SMX_CMD_BYPASS);
wire wr_cr_avail_n= (wcmd_is_order_n & ocr_avail) |
(wcmd_is_bypass_n & bcr_avail);
wire wr_rdy_n= ~wreq_pcmd_ff_empty & wr_cr_avail_n;
reg [1:0] arb_ns, arb_cs;
always @(/*AUTOSENSE*/`SMX_REQARB_RD or `SMX_REQARB_WR or arb_cs
or nxt_xmit or rcmd_is_bypass_n or rcmd_is_order_n
or rd_rdy_n or rwflag or tag_is_valid_n or wcmd_is_bypass_n
or wcmd_is_order_n or wr_rdy_n) begin
rwflag_n= rwflag; // 0= rd, 1= wr
arb_s0: begin // none chosen; rd first
rwflag_n= `SMX_REQARB_RD;
o_enq_n= rcmd_is_order_n & tag_is_valid_n; // q only if valid; (chg'd 121405)
b_enq_n= rcmd_is_bypass_n & tag_is_valid_n; // this will be dropped in siireq interface
rwflag_n= `SMX_REQARB_WR;
o_enq_n= wcmd_is_order_n;
b_enq_n= wcmd_is_bypass_n;
else arb_ns= arb_cs; // no req; do nothing
arb_s1: begin // chosen, wait nxt_xmit, wr first
rwflag_n= `SMX_REQARB_WR;
o_enq_n= wcmd_is_order_n;
b_enq_n= wcmd_is_bypass_n;
rwflag_n= `SMX_REQARB_RD;
o_enq_n= rcmd_is_order_n & tag_is_valid_n;
b_enq_n= rcmd_is_bypass_n & tag_is_valid_n;
arb_ns= arb_s3; // wr still first
arb_s2: begin // chosen, wait nxt_xmit, rd first
rwflag_n= `SMX_REQARB_RD;
o_enq_n= rcmd_is_order_n & tag_is_valid_n;
b_enq_n= rcmd_is_bypass_n & tag_is_valid_n;
rwflag_n= `SMX_REQARB_WR;
o_enq_n= wcmd_is_order_n;
b_enq_n= wcmd_is_bypass_n;
arb_ns= arb_s0; // rd still first
arb_s3: begin // none chosen, wr first
rwflag_n= `SMX_REQARB_WR;
o_enq_n= wcmd_is_order_n;
b_enq_n= wcmd_is_bypass_n;
rwflag_n= `SMX_REQARB_RD;
o_enq_n= rcmd_is_order_n & tag_is_valid_n;
b_enq_n= rcmd_is_bypass_n & tag_is_valid_n;
else arb_ns= arb_cs; // no req; do nothing
always @(posedge clk) begin
if(rst_xmitflag_n) xmitflag<= `SMX_PD 1'b0;
else if(set_xmitflag_n) xmitflag<= `SMX_PD 1'b1;
rwflag<= `SMX_PD rwflag_n;
wire [127:0] wr_hdr_data_n= {wreq_cmdff_rdata[`SMX_CMDFF_POS_CMD],
(wreq_cmdff_rdata[`SMX_CMDFF_POS_ERR] |
{2'h0, |wreq_pcmd_ff_rdata}), // propagate error
wreq_cmdff_rdata[`SMX_CMDFF_POS_ID],
wreq_cmdff_rdata[`SMX_CMDFF_POS_ADDR]};
wire [127:0] rd_hdr_data_n= {rdreq_cmdff_rdata[`SMX_CMDFF_POS_CMD],
rdreq_cmdff_rdata[`SMX_CMDFF_POS_ERR],
rdreq_cmdff_rdata[`SMX_CMDFF_POS_ID],
rdreq_cmdff_rdata[`SMX_CMDFF_POS_ADDR]};
always @(posedge clk) begin
hdr_data<= `SMX_PD (rwflag_n==`SMX_REQARB_WR)? {1'b1, wr_hdr_data_n} : {tag_is_valid_n, rd_hdr_data_n};
bypass<= `SMX_PD (rwflag_n==`SMX_REQARB_WR)? wcmd_is_bypass_n : rcmd_is_bypass_n;
wire wreq_cmdff_rd= wreq_cmdff_rd_n;
wire wreq_pcmd_ff_rd= wreq_pcmd_ff_rd_n;
wire rdreq_cmdff_rd= rdreq_cmdff_rd_n;