design/sys/iop/niu/rtl/niu_txc_drr_context.v

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// OpenSPARC T2 Processor File: niu_txc_drr_context.v
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/*********************************************************************
 *
 *  niu_txc_drr_context.v
 *
 *  DRR Arbiter Context
 *
 *  Orignal Author(s):   Rahoul Puri
 *  Modifier(s):
 *  Project(s):          Neptune
 *
 *  Copyright (c) 2004   Sun Microsystems, Inc.
 *
 *  All Rights Reserved.
 *
 *  This verilog model is the confidential and proprietary property of
 *  Sun Microsystems, Inc., and the possession or use of this model
 *  requires a written license from Sun Microsystems, Inc.
 *
 **********************************************************************/

`include "timescale.v"

module niu_txc_drr_context (
        SysClk,
        Reset_L,
        FlushEngine,

        ClrMaxBurst,        // Clear max burst bit in control register
        NewMaxBurst,        // Max burst bit in control register
        MaxBurst,

        PacketDone,
        PacketByteCount,    // Byte count of the packet that was serviced

        DMA_Reset_Done,
        DMA_EofList,
        AddCreditToContext,
        ClrDeficitForEofList,
        ContextActiveList,
        NextDMAChannel,
        ContextNumber,
        NoDeficit
       );

`include "txc_defines.h"

// Global Signals
input         SysClk;
input         Reset_L;
input         FlushEngine;

// Control Registers
input         ClrMaxBurst;
input         NewMaxBurst;
input  [19:0] MaxBurst;

// Data Fetch State Machine
input         PacketDone;
input  [15:0] PacketByteCount;

// DRR Arbiter State Machine
input         DMA_Reset_Done;
input         DMA_EofList;
input         AddCreditToContext;
input         ClrDeficitForEofList;
input         ContextActiveList;
input  [4:0]  NextDMAChannel;
input  [4:0]  ContextNumber;

output        NoDeficit;

/*--------------------------------------------------------------*/
// Wires & Registers
/*--------------------------------------------------------------*/
wire          addCredit;
wire          updatebyteCount;
wire          updateMaxBurst;

reg    [19:0] contextBurst;
reg    [20:0] byteCount;

/*--------------------------------------------------------------*/
// Parameters and Defines
/*--------------------------------------------------------------*/

/*--------------------------------------------------------------*/
// Zero In Checks
/*--------------------------------------------------------------*/


/*--------------------------------------------------------------*/
// Assigns
/*--------------------------------------------------------------*/

assign NoDeficit = (byteCount < {1'b0, contextBurst});

assign addCredit = (AddCreditToContext & ContextActiveList);

assign updateMaxBurst  = (ClrMaxBurst & NewMaxBurst);

assign updatebyteCount = (PacketDone
                          &&
                          (NextDMAChannel == ContextNumber)
                         );

/*--------------------------------------------------------------*/
// Instantiated Flops
/*--------------------------------------------------------------*/

always @(posedge SysClk)
  if (!Reset_L)            contextBurst <= #`SD 20'h0;
  else if (updateMaxBurst) contextBurst <= #`SD MaxBurst;

always @(posedge SysClk)
  if (!Reset_L)                                byteCount <= #`SD 21'h0;
  else if (FlushEngine)                        byteCount <= #`SD 21'h0;
  else if (DMA_Reset_Done)                     byteCount <= #`SD 21'h0;
  else if (ClrDeficitForEofList & DMA_EofList) byteCount <= #`SD 21'h0;
  else if (addCredit)
    begin
      if (NoDeficit) byteCount <= #`SD 21'h0;
      else           byteCount <= #`SD (byteCount - {1'b0, contextBurst});
    end
  else if (updatebyteCount) byteCount <= #`SD (byteCount
                                               +
                                              {5'h0, PacketByteCount});

endmodule