// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: niu_txc_tdmc_context.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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// it under the terms of the GNU General Public License as published by
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// ========== Copyright Header End ============================================
/*********************************************************************
* Orignal Author(s): Rahoul Puri
* Project(s): Neptune/Niagara 2
* Copyright (c) 2004 Sun Microsystems, Inc.
* This verilog model is the confidential and proprietary property of
* Sun Microsystems, Inc., and the possession or use of this model
* requires a written license from Sun Microsystems, Inc.
**********************************************************************/
module niu_txc_tdmc_context (
input Port0_DMA_inc_head;
input Port0_DMA_reset_done;
input Port0_DMA_mark_bit;
input Port0_DMA_inc_pkt_cnt;
input Port0_SetGetNextDescDMA;
input Port1_DMA_inc_head;
input Port1_DMA_reset_done;
input Port1_DMA_mark_bit;
input Port1_DMA_inc_pkt_cnt;
input Port1_SetGetNextDescDMA;
input Port2_DMA_inc_head;
input Port2_DMA_reset_done;
input Port2_DMA_mark_bit;
input Port2_DMA_inc_pkt_cnt;
input Port2_SetGetNextDescDMA;
input Port3_DMA_inc_head;
input Port3_DMA_reset_done;
input Port3_DMA_mark_bit;
input Port3_DMA_inc_pkt_cnt;
input Port3_SetGetNextDescDMA;
input DMC_TXC_DMA_GotNxtDesc;
output TXC_DMC_DMA_GetNxtDesc;
output TXC_DMC_DMA_inc_head;
output TXC_DMC_DMA_reset_done;
output TXC_DMC_DMA_mark_bit;
output TXC_DMC_DMA_inc_pkt_cnt;
reg TXC_DMC_DMA_GetNxtDesc;
reg TXC_DMC_DMA_inc_head;
reg TXC_DMC_DMA_reset_done;
reg TXC_DMC_DMA_mark_bit;
reg TXC_DMC_DMA_inc_pkt_cnt;
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
assign dma_inc_head = (Port0_DMA_inc_head | Port1_DMA_inc_head
Port2_DMA_inc_head | Port3_DMA_inc_head
assign dma_reset_done = (Port0_DMA_reset_done | Port1_DMA_reset_done
Port2_DMA_reset_done | Port3_DMA_reset_done
assign dma_mark_bit = (Port0_DMA_mark_bit | Port1_DMA_mark_bit
Port2_DMA_mark_bit | Port3_DMA_mark_bit
assign dma_inc_pkt_cnt = (Port0_DMA_inc_pkt_cnt | Port1_DMA_inc_pkt_cnt
Port2_DMA_inc_pkt_cnt | Port3_DMA_inc_pkt_cnt
assign setGetNextDescDMA = (Port3_SetGetNextDescDMA | Port2_SetGetNextDescDMA
Port1_SetGetNextDescDMA | Port0_SetGetNextDescDMA);
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
if (!Reset_L) TXC_DMC_DMA_inc_head <= #`SD 1'b0;
else TXC_DMC_DMA_inc_head <= #`SD dma_inc_head;
if (!Reset_L) TXC_DMC_DMA_reset_done <= #`SD 1'b0;
else TXC_DMC_DMA_reset_done <= #`SD dma_reset_done;
if (!Reset_L) TXC_DMC_DMA_mark_bit <= #`SD 1'b0;
else TXC_DMC_DMA_mark_bit <= #`SD dma_mark_bit;
if (!Reset_L) TXC_DMC_DMA_inc_pkt_cnt <= #`SD 1'b0;
else TXC_DMC_DMA_inc_pkt_cnt <= #`SD dma_inc_pkt_cnt;
if (!Reset_L) TXC_DMC_DMA_GetNxtDesc <= #`SD 1'b0;
else if (setGetNextDescDMA) TXC_DMC_DMA_GetNxtDesc <= #`SD 1'b1;
else if (DMC_TXC_DMA_GotNxtDesc) TXC_DMC_DMA_GetNxtDesc <= #`SD 1'b0;