design/sys/iop/niu/rtl/xpcs_txio.v

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//
// OpenSPARC T2 Processor File: xpcs_txio.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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// ****************************************************************
//
//   Sun Proprietary/Confidential: Internal Use Only
//
// ****************************************************************
//   Design: XPCS Phy Interface Core
//    Block: XPCS Phy Interface Core Top Level
//   Author: Carlos Castil
//
//   Module: xpcs_txio
//     File: xpcs_txio.v
//
//   Description: This block contains 8 channel transmit physical
//                interface to ieee 802.3 clause 48 xpcs.
//
//   Revision History
//   ------------------------------------------------------------
//      Ver   Date      Comments
//   ------------------------------------------------------------
//      1.0   11/12/02  Created
//
// ****************************************************************

module xpcs_txio (
                reset,
                tx_clk,

                tx_byte_0,
                tx_byte_1,
                tx_byte_2,
                tx_byte_3,

                tx_special_0,
                tx_special_1,
                tx_special_2,
                tx_special_3,

                tx_symbol_0,
                tx_symbol_1,
                tx_symbol_2,
                tx_symbol_3

                );

// Interface
input           reset;
input           tx_clk;

input   [7:0]   tx_byte_0;
input   [7:0]   tx_byte_1;
input   [7:0]   tx_byte_2;
input   [7:0]   tx_byte_3;

input           tx_special_0;
input           tx_special_1;
input           tx_special_2;
input           tx_special_3;

output [9:0]    tx_symbol_0;
output [9:0]    tx_symbol_1;
output [9:0]    tx_symbol_2;
output [9:0]    tx_symbol_3;


// lane 0 macro

xpcs_txio_pcs u_lane_0 (
                .reset          (reset),
                .tx_clk         (tx_clk),

                .tx_byte        (tx_byte_0),
                .tx_special     (tx_special_0),

                .tx_symbol      (tx_symbol_0) );

// lane 1 macro

xpcs_txio_pcs u_lane_1 (
                .reset          (reset),
                .tx_clk         (tx_clk),

                .tx_byte        (tx_byte_1),
                .tx_special     (tx_special_1),

                .tx_symbol      (tx_symbol_1) );


// lane 2 macro

xpcs_txio_pcs u_lane_2 (
                .reset          (reset),
                .tx_clk         (tx_clk),

                .tx_byte        (tx_byte_2),
                .tx_special     (tx_special_2),

                .tx_symbol      (tx_symbol_2) );

// lane 3 macro

xpcs_txio_pcs u_lane_3 (
                .reset          (reset),
                .tx_clk         (tx_clk),

                .tx_byte        (tx_byte_3),
                .tx_special     (tx_special_3),

                .tx_symbol      (tx_symbol_3) );


endmodule