design/sys/iop/rtx/synopsys/script/user_cfg.scr

source -echo -verbose $dv_root/design/sys/synopsys/script/project_io_cfg.scr

set rtl_files {\
libs/cl/cl_rtl_ext.v
libs/cl/cl_a1/cl_a1.behV
libs/cl/cl_u1/cl_u1.behV
libs/cl/cl_dp1/cl_dp1.behV
libs/cl/cl_sc1/cl_sc1.behV
libs/cl/cl_mc1/cl_mc1.v

libs/clk/rtl/clkgen_rtx_io2x.v
libs/clk/rtl/clkgen_rtx_io.v

libs/clk/n2_clk_clstr_hdr_cust_l/n2_clk_clstr_hdr_cust/rtl/n2_clk_clstr_hdr_cust.v
libs/clk/n2_clk_pgrid_cust_l/n2_clk_rtx_io_cust/rtl/n2_clk_rtx_io_cust.v
libs/clk/n2_clk_pgrid_cust_l/n2_clk_rtx_io2x_cust/rtl/n2_clk_rtx_io2x_cust.v

libs/n2sram/dp/n2_niu_dp_512x152s_cust_l/n2_niu_dp_512x152s_cust/rtl/n2_niu_dp_512x152s_cust.v
libs/n2sram/dp/n2_niu_dp_1024x152s_cust_l/n2_niu_dp_1024x152s_cust/rtl/n2_niu_dp_1024x152s_cust.v
libs/n2sram/sp/n2_niu_sp_4096x9s_cust_l/n2_niu_sp_4096x9s_cust/rtl/n2_niu_sp_4096x9s_cust.v

libs/n2sram/compiler/physical/n2_com_dp_128x42s_cust_l/n2_com_dp_128x42s_cust/rtl/n2_com_dp_128x42s_cust.v
libs/n2sram/compiler/physical/n2_com_dp_64x148s_cust_l/n2_com_dp_64x148s_cust/rtl/n2_com_dp_64x148s_cust.v
libs/n2sram/cams/n2_niu_tc_128x200s_cust_l/n2_niu_tc_128x200s_cust/rtl/n2_niu_tc_128x200s_cust.v

design/sys/iop/niu/rtl/df1.v
design/sys/iop/niu/rtl/dffe.v
design/sys/iop/niu/rtl/dffr.v
design/sys/iop/niu/rtl/dffre.v

design/sys/iop/niu/rtl/niu_ram_64_146.v
design/sys/iop/niu/rtl/niu_ram_1024_146.v
design/sys/iop/niu/rtl/niu_ram_1024_152.v
design/sys/iop/niu/rtl/niu_cam_128x200.v
design/sys/iop/niu/rtl/niu_ram_s_4096x9.v
design/sys/iop/niu/rtl/niu_ram_128_42.v
design/sys/iop/niu/rtl/niu_ram_64x146.v
design/sys/iop/niu/rtl/niu_ram_1024x152.v
design/sys/iop/niu/rtl/niu_ram_512_146.v

design/sys/iop/niu/rtl/timescale.v
design/sys/iop/niu/rtl/niu_65data_ecc_check.v
design/sys/iop/niu/rtl/niu_65data_ecc_generate.v
design/sys/iop/niu/rtl/niu_65data_ecc_generate_w_err_injection.v
design/sys/iop/niu/rtl/niu_65data_ecc_correct.v
design/sys/iop/niu/rtl/niu_64data_ecc_check.v
design/sys/iop/niu/rtl/niu_64data_ecc_generate.v
design/sys/iop/niu/rtl/niu_dff.v
design/sys/iop/niu/rtl/reset_buffer.v

design/sys/iop/niu/rtl/niu_mb1.v
design/sys/iop/niu/rtl/niu_mb2.v
design/sys/iop/niu/rtl/niu_mb3.v
design/sys/iop/niu/rtl/niu_mb4.v
design/sys/iop/niu/rtl/niu_mb5.v
design/sys/iop/niu/rtl/niu_mb6.v
design/sys/iop/niu/rtl/niu_mb7.v
design/sys/iop/niu/rtl/niu_zcp.h
design/sys/iop/niu/rtl/niu_scam.h
design/sys/iop/niu/rtl/fflp.h

design/sys/iop/niu/rtl/niu_rxc.v
design/sys/iop/niu/rtl/niu_scam_ary.v
design/sys/iop/niu/rtl/niu_scam_ctl.v
design/sys/iop/niu/rtl/niu_scam_enc.v
design/sys/iop/niu/rtl/niu_scam_lib.v
design/sys/iop/niu/rtl/niu_scam_pre.v
design/sys/iop/niu/rtl/niu_tcam.v
design/sys/iop/niu/rtl/niu_ipp.h
design/sys/iop/niu/rtl/niu_ipp_1ke.v
design/sys/iop/niu/rtl/niu_ipp_dat_fifo_1ke.v
design/sys/iop/niu/rtl/niu_ipp_dmc_checker.v
design/sys/iop/niu/rtl/niu_ipp_ffl_arbiter.v
design/sys/iop/niu/rtl/niu_ipp_hdr_fifo.v
design/sys/iop/niu/rtl/niu_ipp_lib.v
design/sys/iop/niu/rtl/niu_ipp_load.v
design/sys/iop/niu/rtl/niu_ipp_pkt_dsc.v
design/sys/iop/niu/rtl/niu_ipp_slv.v
design/sys/iop/niu/rtl/niu_ipp_sum_ctrl.v
design/sys/iop/niu/rtl/niu_ipp_sum_data.v
design/sys/iop/niu/rtl/niu_ipp_sum_lib.v
design/sys/iop/niu/rtl/niu_ipp_sum_unit.v
design/sys/iop/niu/rtl/niu_ipp_sum_lib.h
design/sys/iop/niu/rtl/niu_ipp_top.v
design/sys/iop/niu/rtl/niu_ipp_unload_ctl_1ke.v
design/sys/iop/niu/rtl/niu_ipp_unload_dat.v

design/sys/iop/niu/rtl/fflp.h
design/sys/iop/niu/rtl/fflp.v
design/sys/iop/niu/rtl/fflp_cam_ram.v
design/sys/iop/niu/rtl/fflp_cam_sched.v
design/sys/iop/niu/rtl/fflp_cam_srch.v
design/sys/iop/niu/rtl/fflp_cam_srch_sm.v
design/sys/iop/niu/rtl/fflp_fcram_arb.v
design/sys/iop/niu/rtl/fflp_fcram_cntl.v
design/sys/iop/niu/rtl/fflp_fcram_cntl_sm.v
design/sys/iop/niu/rtl/fflp_fcram_fwd_arb.v
design/sys/iop/niu/rtl/fflp_fcram_sched.v
design/sys/iop/niu/rtl/fflp_fcram_top.v
design/sys/iop/niu/rtl/fflp_fwd_mstr.v
design/sys/iop/niu/rtl/fflp_hdr.v
design/sys/iop/niu/rtl/fflp_flow_fifo.v
design/sys/iop/niu/rtl/fflp_hdr_cntl.v
design/sys/iop/niu/rtl/fflp_hdr_dp.v
design/sys/iop/niu/rtl/fflp_hdr_fifo.v
design/sys/iop/niu/rtl/fflp_merge_func.v
design/sys/iop/niu/rtl/fflp_pio_if.v
design/sys/iop/niu/rtl/fflp_ram_cntl.v
design/sys/iop/niu/rtl/fflp_CRC32_D64.v
design/sys/iop/niu/rtl/fflp_CRC16_D64.v
design/sys/iop/niu/rtl/fflp_hash_func.v
design/sys/iop/niu/rtl/fflp_sync2fc_clk.v
design/sys/iop/niu/rtl/fflp_sync2sys_clk.v

design/sys/iop/niu/rtl/niu_zcp.h
design/sys/iop/niu/rtl/niu_zcp.v
design/sys/iop/niu/rtl/niu_zcp_fflp_intf.v
design/sys/iop/niu/rtl/niu_zcp_ififo_sm.v
design/sys/iop/niu/rtl/niu_zcp_ififo.v
design/sys/iop/niu/rtl/niu_zcp_cfifo8KB.v
design/sys/iop/niu/rtl/niu_zcp_tt.v
design/sys/iop/niu/rtl/niu_zcp_tt_sm.v
design/sys/iop/niu/rtl/niu_zcp_slv.v
design/sys/iop/niu/rtl/niu_zcp_ram_access_sm.v
design/sys/iop/niu/rtl/niu_zcp_handle_decoder.v
design/sys/iop/niu/rtl/niu_zcp_macros.v
design/sys/iop/niu/rtl/niu_zcp_reset_gen.v
design/sys/iop/niu/rtl/niu_zcp_debug.v

design/sys/iop/niu/rtl/txc_defines.h
design/sys/iop/niu/rtl/niu_txc.v
design/sys/iop/niu/rtl/niu_txc_ControlRegs.v
design/sys/iop/niu/rtl/niu_txc_dataFetch.v
design/sys/iop/niu/rtl/niu_txc_drr_arbiter.v
design/sys/iop/niu/rtl/niu_txc_drr_context.v
design/sys/iop/niu/rtl/niu_txc_drr_engine.v
design/sys/iop/niu/rtl/niu_txc_ecc_engine.v
design/sys/iop/niu/rtl/niu_txc_ecc_correct.v
design/sys/iop/niu/rtl/niu_txc_ecc_generate.v
design/sys/iop/niu/rtl/niu_txc_ecc_syndrome.v
design/sys/iop/niu/rtl/niu_txc_mac_transfer.v
design/sys/iop/niu/rtl/niu_txc_packetAssy.v
design/sys/iop/niu/rtl/niu_txc_packetEngine.v
design/sys/iop/niu/rtl/niu_txc_portRequest.v
design/sys/iop/niu/rtl/niu_txc_portRegisters.v
design/sys/iop/niu/rtl/niu_txc_reAligner.v
design/sys/iop/niu/rtl/niu_txc_RegisterControl.v
design/sys/iop/niu/rtl/niu_txc_dmaRegisters.v
design/sys/iop/niu/rtl/niu_txc_reg_defines.h
design/sys/iop/niu/rtl/niu_txc_Reset.v
design/sys/iop/niu/rtl/niu_txc_debug.v
design/sys/iop/niu/rtl/niu_txc_tdmc_ifc.v
design/sys/iop/niu/rtl/niu_txc_tdmc_context.v
design/sys/iop/niu/rtl/niu_txc_mac_ifc.v
design/sys/iop/niu/rtl/niu_txc_meta_resp_ifc.v
design/sys/iop/niu/rtl/niu_txc_tdmc_error.v
design/sys/iop/niu/rtl/niu_txc_clkbuf.v

design/sys/iop/rtx/rtl/rtx_n2_efuhdr1a_p0_ctl.v
design/sys/iop/rtx/rtl/rtx_n2_efuhdr1a_p1_ctl.v
design/sys/iop/rtx/rtl/rtx_n2_efuhdr1b_p0_ctl.v
design/sys/iop/rtx/rtl/rtx_n2_efuhdr1b_p1_ctl.v
design/sys/iop/rtx/rtl/rtx_n2_efuhdr3_p0_ctl.v
design/sys/iop/rtx/rtl/rtx_n2_efuhdr3_p1_ctl.v
design/sys/iop/rtx/rtl/rtx_n2_efuhdr6_ctl.v
design/sys/iop/rtx/rtl/rtx_n2_efuhdr7_p0_ctl.v
design/sys/iop/rtx/rtl/rtx_n2_efuhdr7_p1_ctl.v
design/sys/iop/rtx/rtl/clkgen_rtx.v
design/sys/iop/rtx/rtl/clkgen2x_rtx.v
design/sys/iop/rtx/rtl/rtx_dmo_mux.v
design/sys/iop/rtx/rtl/rtx.v
}

set link_library [concat $link_library \
   dw_foundation.sldb \
]


set mix_files {}
set top_module rtx

set include_paths {\
}

set black_box_libs {}
set black_box_designs {}
set mem_libs {}

set dont_touch_modules {\
n2_niu_dp_1024x152s_cust \
n2_niu_dp_512x152s_cust \
n2_niu_sp_4096x9s_cust \
n2_com_dp_64x148s_cust \
n2_com_dp_128x42s_cust \
n2_niu_tc_128x200s_cust \
}

set compile_effort   "medium"

set compile_flatten_all 1

set compile_no_new_cells_at_top_level false

set default_clk cmp_gclk_c0_rtx
set default_clk_freq  1500
set default_setup_skew  0.0
set default_hold_skew  0.0
set default_clk_transition  0.05
set clk_list {                        \
                { cmp_gclk_c0_rtx    1500.0   0.000   0.000   0.05}        \
}

set ideal_net_list {}
set false_path_list {}
set enforce_input_fanout_one     0
set allow_outport_drive_innodes  1
set skip_scan            0
set add_lockup_latch     false
set chain_count          1
set scanin_port_list     {}
set scanout_port_list    {}
set scanenable_port      global_shift_enable
set has_test_stub        1
set scanenable_pin       test_stub_no_bist/se
set long_chain_so_0_net  long_chain_so_0
set short_chain_so_0_net short_chain_so_0
set so_0_net             so_0
set insert_extra_lockup_latch 0
set extra_lockup_latch_clk_list {}