// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: ifu_cmu_msb_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
wire ftu_thrx_un_cacheable_buf;
wire [2:0] ftu_rep_way_buf;
wire [39:0] ftu_paddr_buf;
wire [44:0] e0_misc_dout;
wire [44:0] e1_misc_dout;
wire [44:0] e2_misc_dout;
wire [44:0] e3_misc_dout;
wire [44:0] e4_misc_dout;
wire [44:0] e5_misc_dout;
wire [44:0] e6_misc_dout;
wire [44:0] e7_misc_dout;
wire e0_phyaddr_reg_scanin;
wire e0_phyaddr_reg_scanout;
wire e1_phyaddr_reg_scanin;
wire e1_phyaddr_reg_scanout;
wire e2_phyaddr_reg_scanin;
wire e2_phyaddr_reg_scanout;
wire e3_phyaddr_reg_scanin;
wire e3_phyaddr_reg_scanout;
wire e4_phyaddr_reg_scanin;
wire e4_phyaddr_reg_scanout;
wire e5_phyaddr_reg_scanin;
wire e5_phyaddr_reg_scanout;
wire e6_phyaddr_reg_scanin;
wire e6_phyaddr_reg_scanout;
wire e7_phyaddr_reg_scanin;
wire e7_phyaddr_reg_scanout;
wire [2:0] cmu_fill_wrway_prebuf;
wire [39:0] cmu_fill_paddr_prebuf;
wire mdp_lsi_nc_bit_prebuf;
wire mdp_lsi_inv_bit_prebuf;
wire [2:0] mdp_lsi_rway_prebuf;
wire [39:0] ifu_l15_addr_din;
wire [39:0] ifu_l15_addr_mux;
wire [39:39] ifu_l15_addr_muxbuf;
wire [4:0] ifu_l15_addr_mux_bit4_0;
wire [38:5] ifu_l15_addr_mux_minbuf;
wire ifu_l15_lat0_scanin;
wire ifu_l15_lat0_scanout;
wire [39:0] ifu_l15_addr_prebuf;
input tcu_pce_ov; // scan signals
input [8:6] l15_spc_cpkt;
input [7:0] ftu_inv_req; //from ftu tsm
input ftu_thrx_un_cacheable;
input [7:0] lsc_req_sel; //selected pending requests
input [7:0] mct_upd_addr; //one-hot signal, selects one MB line to be updated for phys addr
input [7:0] mct_real_wom; // real wom bits
output [7:0] mdp_mbhit_q; // misbuffer hit
output [2:0] mdp_lsi_rway; //MB to LSU
output [39:0] ifu_l15_addr; //MB to lsu
output mdp_lsi_nc_bit; //cacheable bit from MB to CMSB
output mdp_lsi_inv_bit; //cacheable bit from MB to CMSB
//output mdp_lsu_par_bit; //parity bit from MB to ??
output [2:0] cmu_fill_wrway; //MB to ??
output [39:0] cmu_fill_paddr;//MB to lsu
//output mdp_fill_par_bit; //parity bit from MB to ??
ifu_cmu_msb_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0 (
.din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
.dout({se,pce_ov,siclk,soclk})
// buffer ftu data before using it
ifu_cmu_msb_dp_buff_macro__stack_60c__width_44 ftu_data (
.din ({ftu_thrx_un_cacheable, ftu_rep_way[2:0], ftu_paddr[39:0]}),
.dout ({ftu_thrx_un_cacheable_buf, ftu_rep_way_buf[2:0], ftu_paddr_buf[39:0]})
////////////////////////////////////////////////////////////////
// physical adress, cacheable bit, parity bit and replace way
// registers for all entries
////////////////////////////////////////////////////////////////
ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_45 addr_upd_mux0 (
.din1({e0_misc_dout[44:0]}),
.din0({ftu_thrx_un_cacheable_buf, ftu_inv_req[0], ftu_rep_way_buf[2:0], ftu_paddr_buf[39:0]}),
.dout({e0_misc_din[44:0]})
ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_45 addr_upd_mux1 (
.din1({e1_misc_dout[44:0]}),
.din0({ftu_thrx_un_cacheable_buf, ftu_inv_req[1], ftu_rep_way_buf[2:0], ftu_paddr_buf[39:0]}),
.dout({e1_misc_din[44:0]})
ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_45 addr_upd_mux2 (
.din1({e2_misc_dout[44:0]}),
.din0({ftu_thrx_un_cacheable_buf, ftu_inv_req[2], ftu_rep_way_buf[2:0], ftu_paddr_buf[39:0]}),
.dout({e2_misc_din[44:0]})
ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_45 addr_upd_mux3 (
.din1({e3_misc_dout[44:0]}),
.din0({ftu_thrx_un_cacheable_buf, ftu_inv_req[3], ftu_rep_way_buf[2:0], ftu_paddr_buf[39:0]}),
.dout({e3_misc_din[44:0]})
ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_45 addr_upd_mux4 (
.din1({e4_misc_dout[44:0]}),
.din0({ftu_thrx_un_cacheable_buf, ftu_inv_req[4], ftu_rep_way_buf[2:0], ftu_paddr_buf[39:0]}),
.dout({e4_misc_din[44:0]})
ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_45 addr_upd_mux5 (
.din1({e5_misc_dout[44:0]}),
.din0({ftu_thrx_un_cacheable_buf, ftu_inv_req[5], ftu_rep_way_buf[2:0], ftu_paddr_buf[39:0]}),
.dout({e5_misc_din[44:0]})
ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_45 addr_upd_mux6 (
.din1({e6_misc_dout[44:0]}),
.din0({ftu_thrx_un_cacheable_buf, ftu_inv_req[6], ftu_rep_way_buf[2:0], ftu_paddr_buf[39:0]}),
.dout({e6_misc_din[44:0]})
ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_45 addr_upd_mux7 (
.din1({e7_misc_dout[44:0]}),
.din0({ftu_thrx_un_cacheable_buf, ftu_inv_req[7], ftu_rep_way_buf[2:0], ftu_paddr_buf[39:0]}),
.dout({e7_misc_din[44:0]})
ifu_cmu_msb_dp_msff_macro__stack_60c__width_45 e0_phyaddr_reg (
.scan_in(e0_phyaddr_reg_scanin),
.scan_out(e0_phyaddr_reg_scanout),
.din ({e0_misc_din[44:0]}),
.dout({e0_misc_dout[44:0]}),
ifu_cmu_msb_dp_msff_macro__stack_60c__width_45 e1_phyaddr_reg (
.scan_in(e1_phyaddr_reg_scanin),
.scan_out(e1_phyaddr_reg_scanout),
.din ({e1_misc_din[44:0]}),
.dout({e1_misc_dout[44:0]}),
ifu_cmu_msb_dp_msff_macro__stack_60c__width_45 e2_phyaddr_reg (
.scan_in(e2_phyaddr_reg_scanin),
.scan_out(e2_phyaddr_reg_scanout),
.din ({e2_misc_din[44:0]}),
.dout({e2_misc_dout[44:0]}),
ifu_cmu_msb_dp_msff_macro__stack_60c__width_45 e3_phyaddr_reg (
.scan_in(e3_phyaddr_reg_scanin),
.scan_out(e3_phyaddr_reg_scanout),
.din ({e3_misc_din[44:0]}),
.dout({e3_misc_dout[44:0]}),
ifu_cmu_msb_dp_msff_macro__stack_60c__width_45 e4_phyaddr_reg (
.scan_in(e4_phyaddr_reg_scanin),
.scan_out(e4_phyaddr_reg_scanout),
.din ({e4_misc_din[44:0]}),
.dout({e4_misc_dout[44:0]}),
ifu_cmu_msb_dp_msff_macro__stack_60c__width_45 e5_phyaddr_reg (
.scan_in(e5_phyaddr_reg_scanin),
.scan_out(e5_phyaddr_reg_scanout),
.din ({e5_misc_din[44:0]}),
.dout({e5_misc_dout[44:0]}),
ifu_cmu_msb_dp_msff_macro__stack_60c__width_45 e6_phyaddr_reg (
.scan_in(e6_phyaddr_reg_scanin),
.scan_out(e6_phyaddr_reg_scanout),
.din ({e6_misc_din[44:0]}),
.dout({e6_misc_dout[44:0]}),
ifu_cmu_msb_dp_msff_macro__stack_60c__width_45 e7_phyaddr_reg (
.scan_in(e7_phyaddr_reg_scanin),
.scan_out(e7_phyaddr_reg_scanout),
.din ({e7_misc_din[44:0]}), // ifu_lsu_nc_bit_mux, ifu_lsu_rway_mux[2:0]}),
.dout({e7_misc_dout[44:0]}),
.stop(stop) // ifu_lsu_nc_bit , ifu_lsu_rway[2:0]})
////////////////////////////////////////////////////////////////
// never generate a hit if the incoming request is non-cacheable.
// This is taken care of in cmp1.
// never generate a hit if stored entry is non-cacheable, or
// it is a inv_req. This is taken care of in cmp2
////////////////////////////////////////////////////////////////
ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_32 e0_addrhit_cmp1 (
.din1( {1'b0, e0_misc_dout[35:5]}),
.din0( {1'b0, ftu_paddr_buf[35:5]})
ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_32 e1_addrhit_cmp1 (
.din1( {1'b0, e1_misc_dout[35:5]}),
.din0( {1'b0, ftu_paddr_buf[35:5]})
ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_32 e2_addrhit_cmp1 (
.din1( {1'b0, e2_misc_dout[35:5]}),
.din0( {1'b0, ftu_paddr_buf[35:5]})
ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_32 e3_addrhit_cmp1 (
.din1( {1'b0, e3_misc_dout[35:5]}),
.din0( {1'b0, ftu_paddr_buf[35:5]})
ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_32 e4_addrhit_cmp1 (
.din1( {1'b0, e4_misc_dout[35:5]}),
.din0( {1'b0, ftu_paddr_buf[35:5]})
ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_32 e5_addrhit_cmp1 (
.din1( {1'b0, e5_misc_dout[35:5]}),
.din0( {1'b0, ftu_paddr_buf[35:5]})
ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_32 e6_addrhit_cmp1 (
.din1( {1'b0, e6_misc_dout[35:5]}),
.din0( {1'b0, ftu_paddr_buf[35:5]})
ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_32 e7_addrhit_cmp1 (
.din1( {1'b0, e7_misc_dout[35:5]}),
.din0( {1'b0, ftu_paddr_buf[35:5]})
ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_8 e0_addrhit_cmp2 (
.din1({e0_misc_dout[44:43], 1'b0, 1'b0, e0_misc_dout[39:36]}),
.din0({2'b00, 1'b0, ftu_thrx_un_cacheable_buf, ftu_paddr_buf[39:36]})
ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_8 e1_addrhit_cmp2 (
.din1({e1_misc_dout[44:43], 1'b0, 1'b0, e1_misc_dout[39:36]}),
.din0({2'b00, 1'b0, ftu_thrx_un_cacheable_buf, ftu_paddr_buf[39:36]})
ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_8 e2_addrhit_cmp2 (
.din1({e2_misc_dout[44:43], 1'b0, 1'b0, e2_misc_dout[39:36]}),
.din0({2'b00, 1'b0, ftu_thrx_un_cacheable_buf, ftu_paddr_buf[39:36]})
ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_8 e3_addrhit_cmp2 (
.din1({e3_misc_dout[44:43], 1'b0, 1'b0, e3_misc_dout[39:36]}),
.din0({2'b00, 1'b0, ftu_thrx_un_cacheable_buf, ftu_paddr_buf[39:36]})
ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_8 e4_addrhit_cmp2 (
.din1({e4_misc_dout[44:43], 1'b0, 1'b0, e4_misc_dout[39:36]}),
.din0({2'b00, 1'b0, ftu_thrx_un_cacheable_buf, ftu_paddr_buf[39:36]})
ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_8 e5_addrhit_cmp2 (
.din1({e5_misc_dout[44:43], 1'b0, 1'b0, e5_misc_dout[39:36]}),
.din0({2'b00, 1'b0, ftu_thrx_un_cacheable_buf, ftu_paddr_buf[39:36]})
ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_8 e6_addrhit_cmp2 (
.din1({e6_misc_dout[44:43], 1'b0, 1'b0, e6_misc_dout[39:36]}),
.din0({2'b00, 1'b0, ftu_thrx_un_cacheable_buf, ftu_paddr_buf[39:36]})
ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_8 e7_addrhit_cmp2 (
.din1({e7_misc_dout[44:43], 1'b0, 1'b0, e7_misc_dout[39:36]}),
.din0({2'b00, 1'b0, ftu_thrx_un_cacheable_buf, ftu_paddr_buf[39:36]})
ifu_cmu_msb_dp_and_macro__ports_3__stack_2l__width_1 and0 (
ifu_cmu_msb_dp_and_macro__ports_3__stack_2l__width_1 and1 (
ifu_cmu_msb_dp_and_macro__ports_3__stack_2l__width_1 and2 (
ifu_cmu_msb_dp_and_macro__ports_3__stack_2l__width_1 and3 (
ifu_cmu_msb_dp_and_macro__ports_3__stack_2l__width_1 and4 (
ifu_cmu_msb_dp_and_macro__ports_3__stack_2l__width_1 and5 (
ifu_cmu_msb_dp_and_macro__ports_3__stack_2l__width_1 and6 (
ifu_cmu_msb_dp_and_macro__ports_3__stack_2l__width_1 and7 (
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////
// MUX OUT MB data and send it to ftu
////////////////////////////////////////////////////////////////
// Mux out remaing bits based on the return thread id
ifu_cmu_msb_dp_mux_macro__mux_aodec__ports_8__stack_60c__width_43 fillwait_data_mux2 (
.din0({e0_misc_dout[42:0]}),
.din1({e1_misc_dout[42:0]}),
.din2({e2_misc_dout[42:0]}),
.din3({e3_misc_dout[42:0]}),
.din4({e4_misc_dout[42:0]}),
.din5({e5_misc_dout[42:0]}),
.din6({e6_misc_dout[42:0]}),
.din7({e7_misc_dout[42:0]}),
.dout({cmu_fill_wrway_prebuf[2:0], cmu_fill_paddr_prebuf[39:0]})
ifu_cmu_msb_dp_buff_macro__stack_60c__width_43 fillwait_data_buf2 (
.din ({cmu_fill_wrway_prebuf[2:0], cmu_fill_paddr_prebuf[39:0]}),
.dout ({cmu_fill_wrway[2:0], cmu_fill_paddr[39:0]})
// mux out MB data to send request out to gkt
// select based on pending req selected
ifu_cmu_msb_dp_mux_macro__mux_aonpe__ports_8__stack_60c__width_45 cmu_data_mux1 (
.din0(e0_misc_dout[44:0]),
.din1(e1_misc_dout[44:0]),
.din2(e2_misc_dout[44:0]),
.din3(e3_misc_dout[44:0]),
.din4(e4_misc_dout[44:0]),
.din5(e5_misc_dout[44:0]),
.din6(e6_misc_dout[44:0]),
.din7(e7_misc_dout[44:0]),
.dout({mdp_lsi_nc_bit_prebuf, mdp_lsi_inv_bit_prebuf, mdp_lsi_rway_prebuf[2:0], ifu_l15_addr_din[39:0]})
// Mux out incoming request if no pending req
ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_40 ifu_l15_mux0 (
.din1(ftu_paddr_buf[39:0]),
.din0(ifu_l15_addr_din[39:0]),
.dout(ifu_l15_addr_mux[39:0])
// if bit 39 = 1, it indicates a NCU or L2 CSR request.
// if bit 39 = 0, it is a l2 request, and bits 4:0 need to be
ifu_cmu_msb_dp_and_macro__ports_2__stack_60c__width_5 ifu_l15_and_4_0
.din1({5{ifu_l15_addr_muxbuf[39]}}),
.din0(ifu_l15_addr_mux[4:0]),
.dout(ifu_l15_addr_mux_bit4_0[4:0])
ifu_cmu_msb_dp_buff_macro__minbuff_1__stack_60c__width_34 ifu_l15_minbuf (
.din ({ifu_l15_addr_mux[38:5]}),
.dout ({ifu_l15_addr_mux_minbuf[38:5]})
ifu_cmu_msb_dp_msff_macro__stack_60c__width_40 ifu_l15_lat0 (
.scan_in(ifu_l15_lat0_scanin),
.scan_out(ifu_l15_lat0_scanout),
.din ({ifu_l15_addr_muxbuf[39],ifu_l15_addr_mux_minbuf[38:5], ifu_l15_addr_mux_bit4_0[4:0]}),
.dout({ifu_l15_addr_prebuf[39:0]}),
ifu_cmu_msb_dp_buff_macro__stack_60c__width_46 ifu_l15_buf0 (
.din ({ifu_l15_addr_mux[39], mdp_lsi_nc_bit_prebuf, mdp_lsi_inv_bit_prebuf, mdp_lsi_rway_prebuf[2:0], ifu_l15_addr_prebuf[39:0]}),
.dout ({ifu_l15_addr_muxbuf[39], mdp_lsi_nc_bit, mdp_lsi_inv_bit, mdp_lsi_rway[2:0], ifu_l15_addr[39:0]})
assign e0_phyaddr_reg_scanin = scan_in ;
assign e1_phyaddr_reg_scanin = e0_phyaddr_reg_scanout ;
assign e2_phyaddr_reg_scanin = e1_phyaddr_reg_scanout ;
assign e3_phyaddr_reg_scanin = e2_phyaddr_reg_scanout ;
assign e4_phyaddr_reg_scanin = e3_phyaddr_reg_scanout ;
assign e5_phyaddr_reg_scanin = e4_phyaddr_reg_scanout ;
assign e6_phyaddr_reg_scanin = e5_phyaddr_reg_scanout ;
assign e7_phyaddr_reg_scanin = e6_phyaddr_reg_scanout ;
assign ifu_l15_lat0_scanin = e7_phyaddr_reg_scanout ;
assign scan_out = ifu_l15_lat0_scanout ;
module ifu_cmu_msb_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 (
module ifu_cmu_msb_dp_buff_macro__stack_60c__width_44 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_45 (
// any PARAMS parms go into naming of macro
module ifu_cmu_msb_dp_msff_macro__stack_60c__width_45 (
.so({so[43:0],scan_out}),
// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
module ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_32 (
// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
module ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_8 (
// and macro for ports = 2,3,4
module ifu_cmu_msb_dp_and_macro__ports_3__stack_2l__width_1 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module ifu_cmu_msb_dp_mux_macro__mux_aodec__ports_8__stack_60c__width_43 (
module ifu_cmu_msb_dp_buff_macro__stack_60c__width_43 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module ifu_cmu_msb_dp_mux_macro__mux_aonpe__ports_8__stack_60c__width_45 (
cl_dp1_muxbuff8_8x c0_0 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_40 (
// and macro for ports = 2,3,4
module ifu_cmu_msb_dp_and_macro__ports_2__stack_60c__width_5 (
module ifu_cmu_msb_dp_buff_macro__minbuff_1__stack_60c__width_34 (
// any PARAMS parms go into naming of macro
module ifu_cmu_msb_dp_msff_macro__stack_60c__width_40 (
.so({so[38:0],scan_out}),
module ifu_cmu_msb_dp_buff_macro__stack_60c__width_46 (