// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: ifu_ftu_ctx_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
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// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
wire tlu_tl_gt_0_reg_scanin;
wire tlu_tl_gt_0_reg_scanout;
wire [7:0] gt_t_zero_to_buf;
wire lsu_ifu_data_reg_scanin;
wire lsu_ifu_data_reg_scanout;
wire [12:0] ifu_ctx_data_ff;
wire [13:0] next_thr0_cnxt_0_data;
wire [13:0] next_thr0_cnxt_1_data;
wire [13:0] next_thr1_cnxt_0_data;
wire [13:0] next_thr1_cnxt_1_data;
wire [13:0] next_thr2_cnxt_0_data;
wire [13:0] next_thr2_cnxt_1_data;
wire [13:0] next_thr3_cnxt_0_data;
wire [13:0] next_thr3_cnxt_1_data;
wire [13:0] next_thr4_cnxt_0_data;
wire [13:0] next_thr4_cnxt_1_data;
wire [13:0] next_thr5_cnxt_0_data;
wire [13:0] next_thr5_cnxt_1_data;
wire [13:0] next_thr6_cnxt_0_data;
wire [13:0] next_thr6_cnxt_1_data;
wire [13:0] next_thr7_cnxt_0_data;
wire [13:0] next_thr7_cnxt_1_data;
wire thr0_cntx_0_reg_wmr_scanin;
wire thr0_cntx_0_reg_wmr_scanout;
wire [7:0] ctx_gt_zero_0_;
wire [12:0] thr0_cntx_0_q;
wire thr0_cntx_1_reg_wmr_scanin;
wire thr0_cntx_1_reg_wmr_scanout;
wire [12:0] thr0_cntx_1_q;
wire thr1_cntx_0_reg_wmr_scanin;
wire thr1_cntx_0_reg_wmr_scanout;
wire [12:0] thr1_cntx_0_q;
wire thr1_cntx_1_reg_wmr_scanin;
wire thr1_cntx_1_reg_wmr_scanout;
wire [12:0] thr1_cntx_1_q;
wire thr2_cntx_0_reg_wmr_scanin;
wire thr2_cntx_0_reg_wmr_scanout;
wire [12:0] thr2_cntx_0_q;
wire thr2_cntx_1_reg_wmr_scanin;
wire thr2_cntx_1_reg_wmr_scanout;
wire [12:0] thr2_cntx_1_q;
wire thr3_cntx_0_reg_wmr_scanin;
wire thr3_cntx_0_reg_wmr_scanout;
wire [12:0] thr3_cntx_0_q;
wire thr3_cntx_1_reg_wmr_scanin;
wire thr3_cntx_1_reg_wmr_scanout;
wire [12:0] thr3_cntx_1_q;
wire thr4_cntx_0_reg_wmr_scanin;
wire thr4_cntx_0_reg_wmr_scanout;
wire [12:0] thr4_cntx_0_q;
wire thr4_cntx_1_reg_wmr_scanin;
wire thr4_cntx_1_reg_wmr_scanout;
wire [12:0] thr4_cntx_1_q;
wire thr5_cntx_0_reg_wmr_scanin;
wire thr5_cntx_0_reg_wmr_scanout;
wire [12:0] thr5_cntx_0_q;
wire thr5_cntx_1_reg_wmr_scanin;
wire thr5_cntx_1_reg_wmr_scanout;
wire [12:0] thr5_cntx_1_q;
wire thr6_cntx_0_reg_wmr_scanin;
wire thr6_cntx_0_reg_wmr_scanout;
wire [12:0] thr6_cntx_0_q;
wire thr6_cntx_1_reg_wmr_scanin;
wire thr6_cntx_1_reg_wmr_scanout;
wire [12:0] thr6_cntx_1_q;
wire thr7_cntx_0_reg_wmr_scanin;
wire thr7_cntx_0_reg_wmr_scanout;
wire [12:0] thr7_cntx_0_q;
wire thr7_cntx_1_reg_wmr_scanin;
wire thr7_cntx_1_reg_wmr_scanout;
wire [12:0] thr7_cntx_1_q;
wire [12:0] ctx_curr_cntx_0_to_buf;
wire [12:0] ctx_curr_cntx_1_to_buf;
wire [13:0] ctx_cntx_0_to_write_to_buf;
wire [13:0] ctx_cntx_1_to_write_to_buf;
input tcu_pce_ov; // scan signals
input [12:0] lsu_ifu_ctxt_data;
input agc_thr0_cntx_0_sel_ff;
input agc_thr0_cntx_1_sel_ff;
input agc_thr1_cntx_0_sel_ff;
input agc_thr1_cntx_1_sel_ff;
input agc_thr2_cntx_0_sel_ff;
input agc_thr2_cntx_1_sel_ff;
input agc_thr3_cntx_0_sel_ff;
input agc_thr3_cntx_1_sel_ff;
input agc_thr4_cntx_0_sel_ff;
input agc_thr4_cntx_1_sel_ff;
input agc_thr5_cntx_0_sel_ff;
input agc_thr5_cntx_1_sel_ff;
input agc_thr6_cntx_0_sel_ff;
input agc_thr6_cntx_1_sel_ff;
input agc_thr7_cntx_0_sel_ff;
input agc_thr7_cntx_1_sel_ff;
input [1:0] agc_thr0_cntx_0_sel;
input [1:0] agc_thr0_cntx_1_sel;
input [1:0] agc_thr1_cntx_0_sel;
input [1:0] agc_thr1_cntx_1_sel;
input [1:0] agc_thr2_cntx_0_sel;
input [1:0] agc_thr2_cntx_1_sel;
input [1:0] agc_thr3_cntx_0_sel;
input [1:0] agc_thr3_cntx_1_sel;
input [1:0] agc_thr4_cntx_0_sel;
input [1:0] agc_thr4_cntx_1_sel;
input [1:0] agc_thr5_cntx_0_sel;
input [1:0] agc_thr5_cntx_1_sel;
input [1:0] agc_thr6_cntx_0_sel;
input [1:0] agc_thr6_cntx_1_sel;
input [1:0] agc_thr7_cntx_0_sel;
input [1:0] agc_thr7_cntx_1_sel;
input [7:0] ftp_itb_fetch_thr_bf;
input [7:0] itc_thr_to_write;
input ftp_itlb_probe_req_l;
output [12:0] ctx_curr_cntx_0_bf;
output [12:0] ctx_curr_cntx_1_bf;
output [13:0] ctx_cntx_0_to_write_bf;
output [13:0] ctx_cntx_1_to_write_bf;
// assign pce_ov = tcu_pce_ov;
// assign siclk = spc_aclk;
// assign soclk = spc_bclk;
// assign muxtst = tcu_muxtest;
ifu_ftu_ctx_dp_buff_macro__dbuff_32x__stack_none__width_4 test_rep0 (
.din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
.dout({se,pce_ov,siclk,soclk})
ifu_ftu_ctx_dp_msff_macro__stack_14c__width_8 tlu_tl_gt_0_reg (
.scan_in(tlu_tl_gt_0_reg_scanin),
.scan_out(tlu_tl_gt_0_reg_scanout),
.din ( tlu_tl_gt_0[7:0]),
.dout( gt_t_zero_to_buf[7:0] ),
ifu_ftu_ctx_dp_buff_macro__stack_14c__width_8 tlu_tl_gt_0_buf (
.din(gt_t_zero_to_buf[7:0]),
ifu_ftu_ctx_dp_msff_macro__stack_14c__width_13 lsu_ifu_data_reg (
.scan_in(lsu_ifu_data_reg_scanin),
.scan_out(lsu_ifu_data_reg_scanout),
.din ( lsu_ifu_ctxt_data[12:0]),
.dout( ifu_ctx_data_ff[12:0] ),
ifu_ftu_ctx_dp_prty_macro__width_16 pgen_lsu_ctxt (
.din ({1'b0,ifu_ctx_data_ff[12:0],2'b00}),
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr0_cntx_0_parity_mux (
.din0( prty_ctxt), // new parity
.din1( thr0_cntx_0[13]), // Hold the old value
.sel0( agc_thr0_cntx_0_sel_ff),
.dout( thr0_prty_ctx_0 ));
ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr0_cntx_1_parity_mux (
.din0( prty_ctxt), // new parity
.din1( thr0_cntx_1[13]), // Hold the old value
.sel0( agc_thr0_cntx_1_sel_ff),
.dout( thr0_prty_ctx_1 ));
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr1_cntx_0_parity_mux (
.din0( prty_ctxt), // new parity
.din1( thr1_cntx_0[13]), // Hold the old value
.sel0( agc_thr1_cntx_0_sel_ff),
.dout( thr1_prty_ctx_0 ));
ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr1_cntx_1_parity_mux (
.din0( prty_ctxt), // new parity
.din1( thr1_cntx_1[13]), // Hold the old value
.sel0( agc_thr1_cntx_1_sel_ff),
.dout( thr1_prty_ctx_1 ));
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr2_cntx_0_parity_mux (
.din0( prty_ctxt), // new parity
.din1( thr2_cntx_0[13]), // Hold the old value
.sel0( agc_thr2_cntx_0_sel_ff),
.dout( thr2_prty_ctx_0 ));
ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr2_cntx_1_parity_mux (
.din0( prty_ctxt), // new parity
.din1( thr2_cntx_1[13]), // Hold the old value
.sel0( agc_thr2_cntx_1_sel_ff),
.dout( thr2_prty_ctx_1 ));
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr3_cntx_0_parity_mux (
.din0( prty_ctxt), // new parity
.din1( thr3_cntx_0[13]), // Hold the old value
.sel0( agc_thr3_cntx_0_sel_ff),
.dout( thr3_prty_ctx_0 ));
ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr3_cntx_1_parity_mux (
.din0( prty_ctxt), // new parity
.din1( thr3_cntx_1[13]), // Hold the old value
.sel0( agc_thr3_cntx_1_sel_ff),
.dout( thr3_prty_ctx_1 ));
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr4_cntx_0_parity_mux (
.din0( prty_ctxt), // new parity
.din1( thr4_cntx_0[13]), // Hold the old value
.sel0( agc_thr4_cntx_0_sel_ff),
.dout( thr4_prty_ctx_0 ));
ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr4_cntx_1_parity_mux (
.din0( prty_ctxt), // new parity
.din1( thr4_cntx_1[13]), // Hold the old value
.sel0( agc_thr4_cntx_1_sel_ff),
.dout( thr4_prty_ctx_1 ));
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr5_cntx_0_parity_mux (
.din0( prty_ctxt), // new parity
.din1( thr5_cntx_0[13]), // Hold the old value
.sel0( agc_thr5_cntx_0_sel_ff),
.dout( thr5_prty_ctx_0 ));
ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr5_cntx_1_parity_mux (
.din0( prty_ctxt), // new parity
.din1( thr5_cntx_1[13]), // Hold the old value
.sel0( agc_thr5_cntx_1_sel_ff),
.dout( thr5_prty_ctx_1 ));
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr6_cntx_0_parity_mux (
.din0( prty_ctxt), // new parity
.din1( thr6_cntx_0[13]), // Hold the old value
.sel0( agc_thr6_cntx_0_sel_ff),
.dout( thr6_prty_ctx_0 ));
ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr6_cntx_1_parity_mux (
.din0( prty_ctxt), // new parity
.din1( thr6_cntx_1[13]), // Hold the old value
.sel0( agc_thr6_cntx_1_sel_ff),
.dout( thr6_prty_ctx_1 ));
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr7_cntx_0_parity_mux (
.din0( prty_ctxt), // new parity
.din1( thr7_cntx_0[13]), // Hold the old value
.sel0( agc_thr7_cntx_0_sel_ff),
.dout( thr7_prty_ctx_0 ));
ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr7_cntx_1_parity_mux (
.din0( prty_ctxt), // new parity
.din1( thr7_cntx_1[13]), // Hold the old value
.sel0( agc_thr7_cntx_1_sel_ff),
.dout( thr7_prty_ctx_1 ));
////////////////////////////////////////////////
// Thread 0 context muxing //
////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr0_cntx_0_mux (
.din0( {1'b0 ,lsu_ifu_ctxt_data[12:0]}), // new context from lsu
.din1( {thr0_prty_ctx_0, thr0_cntx_0[12:0]}), // Hold the old context
.sel0( agc_thr0_cntx_0_sel[0]),
.sel1( agc_thr0_cntx_0_sel[1]),
.dout( next_thr0_cnxt_0_data[13:0] ));
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr0_cntx_1_mux (
.din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu
.din1( {thr0_prty_ctx_1, thr0_cntx_1[12:0]}), // Hold the old context
.sel0( agc_thr0_cntx_1_sel[0]),
.sel1( agc_thr0_cntx_1_sel[1]),
.dout( next_thr0_cnxt_1_data[13:0] ));
////////////////////////////////////////////////
// Thread 1 context muxing //
////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr1_cntx_0_mux (
.din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu
.din1( {thr1_prty_ctx_0, thr1_cntx_0[12:0]}), // Hold the old context
.sel0( agc_thr1_cntx_0_sel[0]),
.sel1( agc_thr1_cntx_0_sel[1]),
.dout( next_thr1_cnxt_0_data[13:0] ));
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr1_cntx_1_mux (
.din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu
.din1( {thr1_prty_ctx_1, thr1_cntx_1[12:0]}), // Hold the old context
.sel0( agc_thr1_cntx_1_sel[0]),
.sel1( agc_thr1_cntx_1_sel[1]),
.dout( next_thr1_cnxt_1_data[13:0] ));
////////////////////////////////////////////////
// Thread 2 context muxing //
////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr2_cntx_0_mux (
.din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu
.din1( {thr2_prty_ctx_0, thr2_cntx_0[12:0]}), // Hold the old context
.sel0( agc_thr2_cntx_0_sel[0]),
.sel1( agc_thr2_cntx_0_sel[1]),
.dout( next_thr2_cnxt_0_data[13:0] ));
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr2_cntx_1_mux (
.din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu
.din1( {thr2_prty_ctx_1, thr2_cntx_1[12:0]}), // Hold the old context
.sel0( agc_thr2_cntx_1_sel[0]),
.sel1( agc_thr2_cntx_1_sel[1]),
.dout( next_thr2_cnxt_1_data[13:0] ));
////////////////////////////////////////////////
// Thread 3 context muxing //
////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr3_cntx_0_mux (
.din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu
.din1( {thr3_prty_ctx_0, thr3_cntx_0[12:0]}), // Hold the old context
.sel0( agc_thr3_cntx_0_sel[0]),
.sel1( agc_thr3_cntx_0_sel[1]),
.dout( next_thr3_cnxt_0_data[13:0] ));
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr3_cntx_1_mux (
.din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu
.din1( {thr3_prty_ctx_1, thr3_cntx_1[12:0]}), // Hold the old context
.sel0( agc_thr3_cntx_1_sel[0]),
.sel1( agc_thr3_cntx_1_sel[1]),
.dout( next_thr3_cnxt_1_data[13:0] ));
////////////////////////////////////////////////
// Thread 4 context muxing //
////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr4_cntx_0_mux (
.din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu
.din1( {thr4_prty_ctx_0, thr4_cntx_0[12:0]}), // Hold the old context
.sel0( agc_thr4_cntx_0_sel[0]),
.sel1( agc_thr4_cntx_0_sel[1]),
.dout( next_thr4_cnxt_0_data[13:0] ));
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr4_cntx_1_mux (
.din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu
.din1( {thr4_prty_ctx_1, thr4_cntx_1[12:0]}), // Hold the old context
.sel0( agc_thr4_cntx_1_sel[0]),
.sel1( agc_thr4_cntx_1_sel[1]),
.dout( next_thr4_cnxt_1_data[13:0] ));
////////////////////////////////////////////////
// Thread 5 context muxing //
////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr5_cntx_0_mux (
.din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu
.din1( {thr5_prty_ctx_0, thr5_cntx_0[12:0]}), // Hold the old context
.sel0( agc_thr5_cntx_0_sel[0]),
.sel1( agc_thr5_cntx_0_sel[1]),
.dout( next_thr5_cnxt_0_data[13:0] ));
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr5_cntx_1_mux (
.din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu
.din1( {thr5_prty_ctx_1, thr5_cntx_1[12:0]}), // Hold the old context
.sel0( agc_thr5_cntx_1_sel[0]),
.sel1( agc_thr5_cntx_1_sel[1]),
.dout( next_thr5_cnxt_1_data[13:0] ));
////////////////////////////////////////////////
// Thread 6 context muxing //
////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr6_cntx_0_mux (
.din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu
.din1( {thr6_prty_ctx_0, thr6_cntx_0[12:0]}), // Hold the old context
.sel0( agc_thr6_cntx_0_sel[0]),
.sel1( agc_thr6_cntx_0_sel[1]),
.dout( next_thr6_cnxt_0_data[13:0] ));
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr6_cntx_1_mux (
.din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu
.din1( {thr6_prty_ctx_1, thr6_cntx_1[12:0]}), // Hold the old context
.sel0( agc_thr6_cntx_1_sel[0]),
.sel1( agc_thr6_cntx_1_sel[1]),
.dout( next_thr6_cnxt_1_data[13:0] ));
////////////////////////////////////////////////
// Thread 7 context muxing //
////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr7_cntx_0_mux (
.din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu
.din1( {thr7_prty_ctx_0, thr7_cntx_0[12:0]}), // Hold the old context
.sel0( agc_thr7_cntx_0_sel[0]),
.sel1( agc_thr7_cntx_0_sel[1]),
.dout( next_thr7_cnxt_0_data[13:0] ));
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr7_cntx_1_mux (
.din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu
.din1( {thr7_prty_ctx_1, thr7_cntx_1[12:0]}), // Hold the old context
.sel0( agc_thr7_cntx_1_sel[0]),
.sel1( agc_thr7_cntx_1_sel[1]),
.dout( next_thr7_cnxt_1_data[13:0] ));
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
////////////////////////////////////
// Thread 0 context registers //
////////////////////////////////////
ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr0_cntx_0_reg ( // FS:wmr_protect
.scan_in(thr0_cntx_0_reg_wmr_scanin),
.scan_out(thr0_cntx_0_reg_wmr_scanout),
.din ( next_thr0_cnxt_0_data[13:0]),
.dout( thr0_cntx_0[13:0] ),
// assign thr0_cntx_0_q[13:0] = thr0_cntx_0[13:0] & {13{~gt_t_zero[0]}} ;
ifu_ftu_ctx_dp_nand_macro__ports_2__stack_14c__width_8 gt_z_nand (
.din1({8{ftp_itlb_probe_req_l}}),
.dout(ctx_gt_zero_0_[7:0])
ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr0_cntx_0_and (
.din0({13{ctx_gt_zero_0_[0]}}),
.din1(thr0_cntx_0[12:0]),
.dout(thr0_cntx_0_q[12:0])
ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr0_cntx_1_reg ( // FS:wmr_protect
.scan_in(thr0_cntx_1_reg_wmr_scanin),
.scan_out(thr0_cntx_1_reg_wmr_scanout),
.din ( next_thr0_cnxt_1_data[13:0]),
.dout( thr0_cntx_1[13:0] ),
ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr0_cntx_1_and (
.din0({13{ctx_gt_zero_0_[0]}}),
.din1(thr0_cntx_1[12:0]),
.dout(thr0_cntx_1_q[12:0])
// assign thr0_cntx_1_q[13:0] = thr0_cntx_1[13:0] & {13{~gt_t_zero[0]}} ;
////////////////////////////////////
// Thread 1 context registers //
////////////////////////////////////
ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr1_cntx_0_reg ( // FS:wmr_protect
.scan_in(thr1_cntx_0_reg_wmr_scanin),
.scan_out(thr1_cntx_0_reg_wmr_scanout),
.din ( next_thr1_cnxt_0_data[13:0]),
.dout( thr1_cntx_0[13:0] ),
// assign thr1_cntx_0_q[13:0] = thr1_cntx_0[13:0] & {13{~gt_t_zero[1]}} ;
ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr1_cntx_0_and (
.din0({13{ctx_gt_zero_0_[1]}}),
.din1(thr1_cntx_0[12:0]),
.dout(thr1_cntx_0_q[12:0])
ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr1_cntx_1_reg ( // FS:wmr_protect
.scan_in(thr1_cntx_1_reg_wmr_scanin),
.scan_out(thr1_cntx_1_reg_wmr_scanout),
.din ( next_thr1_cnxt_1_data[13:0]),
.dout( thr1_cntx_1[13:0] ),
// assign thr1_cntx_1_q[13:0] = thr1_cntx_1[13:0] & {13{~gt_t_zero[1]}} ;
ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr1_cntx_1_and (
.din0({13{ctx_gt_zero_0_[1]}}),
.din1(thr1_cntx_1[12:0]),
.dout(thr1_cntx_1_q[12:0])
////////////////////////////////////
// Thread 2 context registers //
////////////////////////////////////
ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr2_cntx_0_reg ( // FS:wmr_protect
.scan_in(thr2_cntx_0_reg_wmr_scanin),
.scan_out(thr2_cntx_0_reg_wmr_scanout),
.din ( next_thr2_cnxt_0_data[13:0]),
.dout( thr2_cntx_0[13:0] ),
// assign thr2_cntx_0_q[13:0] = thr2_cntx_0[13:0] & {13{~gt_t_zero[2]}} ;
ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr2_cntx_0_and (
.din0({13{ctx_gt_zero_0_[2]}}),
.din1(thr2_cntx_0[12:0]),
.dout(thr2_cntx_0_q[12:0])
ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr2_cntx_1_reg ( // FS:wmr_protect
.scan_in(thr2_cntx_1_reg_wmr_scanin),
.scan_out(thr2_cntx_1_reg_wmr_scanout),
.din ( next_thr2_cnxt_1_data[13:0]),
.dout( thr2_cntx_1[13:0] ),
// assign thr2_cntx_1_q[13:0] = thr2_cntx_1[13:0] & {13{~gt_t_zero[2]}} ;
ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr2_cntx_1_and (
.din0({13{ctx_gt_zero_0_[2]}}),
.din1(thr2_cntx_1[12:0]),
.dout(thr2_cntx_1_q[12:0])
////////////////////////////////////
// Thread 3 context registers //
////////////////////////////////////
ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr3_cntx_0_reg ( // FS:wmr_protect
.scan_in(thr3_cntx_0_reg_wmr_scanin),
.scan_out(thr3_cntx_0_reg_wmr_scanout),
.din ( next_thr3_cnxt_0_data[13:0]),
.dout( thr3_cntx_0[13:0] ),
// assign thr3_cntx_0_q[13:0] = thr3_cntx_0[13:0] & {13{~gt_t_zero[3]}} ;
ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr3_cntx_0_and (
.din0({13{ctx_gt_zero_0_[3]}}),
.din1(thr3_cntx_0[12:0]),
.dout(thr3_cntx_0_q[12:0])
ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr3_cntx_1_reg ( // FS:wmr_protect
.scan_in(thr3_cntx_1_reg_wmr_scanin),
.scan_out(thr3_cntx_1_reg_wmr_scanout),
.din ( next_thr3_cnxt_1_data[13:0]),
.dout( thr3_cntx_1[13:0] ),
// assign thr3_cntx_1_q[13:0] = thr3_cntx_1[13:0] & {13{~gt_t_zero[3]}} ;
ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr3_cntx_1_and (
.din0({13{ctx_gt_zero_0_[3]}}),
.din1(thr3_cntx_1[12:0]),
.dout(thr3_cntx_1_q[12:0])
////////////////////////////////////
// Thread 4 context registers //
////////////////////////////////////
ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr4_cntx_0_reg ( // FS:wmr_protect
.scan_in(thr4_cntx_0_reg_wmr_scanin),
.scan_out(thr4_cntx_0_reg_wmr_scanout),
.din ( next_thr4_cnxt_0_data[13:0]),
.dout( thr4_cntx_0[13:0] ),
// assign thr4_cntx_0_q[13:0] = thr4_cntx_0[13:0] & {13{~gt_t_zero[4]}} ;
ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr4_cntx_0_and (
.din0({13{ctx_gt_zero_0_[4]}}),
.din1(thr4_cntx_0[12:0]),
.dout(thr4_cntx_0_q[12:0])
ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr4_cntx_1_reg ( // FS:wmr_protect
.scan_in(thr4_cntx_1_reg_wmr_scanin),
.scan_out(thr4_cntx_1_reg_wmr_scanout),
.din ( next_thr4_cnxt_1_data[13:0]),
.dout( thr4_cntx_1[13:0] ),
// assign thr4_cntx_1_q[13:0] = thr4_cntx_1[13:0] & {13{~gt_t_zero[4]}} ;
ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr4_cntx_1_and (
.din0({13{ctx_gt_zero_0_[4]}}),
.din1(thr4_cntx_1[12:0]),
.dout(thr4_cntx_1_q[12:0])
////////////////////////////////////
// Thread 5 context registers //
////////////////////////////////////
ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr5_cntx_0_reg ( // FS:wmr_protect
.scan_in(thr5_cntx_0_reg_wmr_scanin),
.scan_out(thr5_cntx_0_reg_wmr_scanout),
.din ( next_thr5_cnxt_0_data[13:0]),
.dout( thr5_cntx_0[13:0] ),
// assign thr5_cntx_0_q[13:0] = thr5_cntx_0[13:0] & {13{~gt_t_zero[5]}} ;
ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr5_cntx_0_and (
.din0({13{ctx_gt_zero_0_[5]}}),
.din1(thr5_cntx_0[12:0]),
.dout(thr5_cntx_0_q[12:0])
ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr5_cntx_1_reg ( // FS:wmr_protect
.scan_in(thr5_cntx_1_reg_wmr_scanin),
.scan_out(thr5_cntx_1_reg_wmr_scanout),
.din ( next_thr5_cnxt_1_data[13:0]),
.dout( thr5_cntx_1[13:0] ),
// assign thr5_cntx_1_q[13:0] = thr5_cntx_1[13:0] & {13{~gt_t_zero[5]}} ;
ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr5_cntx_1_and (
.din0({13{ctx_gt_zero_0_[5]}}),
.din1(thr5_cntx_1[12:0]),
.dout(thr5_cntx_1_q[12:0])
////////////////////////////////////
// Thread 6 context registers //
////////////////////////////////////
ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr6_cntx_0_reg ( // FS:wmr_protect
.scan_in(thr6_cntx_0_reg_wmr_scanin),
.scan_out(thr6_cntx_0_reg_wmr_scanout),
.din ( next_thr6_cnxt_0_data[13:0]),
.dout( thr6_cntx_0[13:0] ),
// assign thr6_cntx_0_q[13:0] = thr6_cntx_0[13:0] & {13{~gt_t_zero[6]}} ;
ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr6_cntx_0_and (
.din0({13{ctx_gt_zero_0_[6]}}),
.din1(thr6_cntx_0[12:0]),
.dout(thr6_cntx_0_q[12:0])
ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr6_cntx_1_reg ( // FS:wmr_protect
.scan_in(thr6_cntx_1_reg_wmr_scanin),
.scan_out(thr6_cntx_1_reg_wmr_scanout),
.din ( next_thr6_cnxt_1_data[13:0]),
.dout( thr6_cntx_1[13:0] ),
// assign thr6_cntx_1_q[13:0] = thr6_cntx_1[13:0] & {13{~gt_t_zero[6]}} ;
ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr6_cntx_1_and (
.din0({13{ctx_gt_zero_0_[6]}}),
.din1(thr6_cntx_1[12:0]),
.dout(thr6_cntx_1_q[12:0])
////////////////////////////////////
// Thread 7 context registers //
////////////////////////////////////
ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr7_cntx_0_reg ( // FS:wmr_protect
.scan_in(thr7_cntx_0_reg_wmr_scanin),
.scan_out(thr7_cntx_0_reg_wmr_scanout),
.din ( next_thr7_cnxt_0_data[13:0]),
.dout( thr7_cntx_0[13:0] ),
// assign thr7_cntx_0_q[13:0] = thr7_cntx_0[13:0] & {13{~gt_t_zero[7]}} ;
ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr7_cntx_0_and (
.din0({13{ctx_gt_zero_0_[7]}}),
.din1(thr7_cntx_0[12:0]),
.dout(thr7_cntx_0_q[12:0])
ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr7_cntx_1_reg ( // FS:wmr_protect
.scan_in(thr7_cntx_1_reg_wmr_scanin),
.scan_out(thr7_cntx_1_reg_wmr_scanout),
.din ( next_thr7_cnxt_1_data[13:0]),
.dout( thr7_cntx_1[13:0] ),
// assign thr7_cntx_1_q[13:0] = thr7_cntx_1[13:0] & {13{~gt_t_zero[7]}} ;
ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr7_cntx_1_and (
.din0({13{ctx_gt_zero_0_[7]}}),
.din1(thr7_cntx_1[12:0]),
.dout(thr7_cntx_1_q[12:0])
/////////////////////////////////////////////////////////////////////
// Mux out the current context for the thread currently in bf //
/////////////////////////////////////////////////////////////////////
//buff_macro tst_mux_rep0 (width=1,dbuff=24x) (
//.dout( tcu_muxtest_rep0 ));
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_8__stack_14c__width_13 curr_cntx_0_mux (
.din0( thr0_cntx_0_q[12:0]), //
.din1( thr1_cntx_0_q[12:0]), //
.din2( thr2_cntx_0_q[12:0]), //
.din3( thr3_cntx_0_q[12:0]), //
.din4( thr4_cntx_0_q[12:0]), //
.din5( thr5_cntx_0_q[12:0]), //
.din6( thr6_cntx_0_q[12:0]), //
.din7( thr7_cntx_0_q[12:0]), //
// .muxtst (tcu_muxtest_rep0),
.sel0( ftp_itb_fetch_thr_bf[0]),
.sel1( ftp_itb_fetch_thr_bf[1]),
.sel2( ftp_itb_fetch_thr_bf[2]),
.sel3( ftp_itb_fetch_thr_bf[3]),
.sel4( ftp_itb_fetch_thr_bf[4]),
.sel5( ftp_itb_fetch_thr_bf[5]),
.sel6( ftp_itb_fetch_thr_bf[6]),
.sel7( ftp_itb_fetch_thr_bf[7]),
.dout( ctx_curr_cntx_0_to_buf[12:0] ));
ifu_ftu_ctx_dp_buff_macro__stack_14c__width_13 curr_cntx_0_buff (
.din(ctx_curr_cntx_0_to_buf[12:0]),
.dout(ctx_curr_cntx_0_bf[12:0]));
//assign ctx_curr_cntx_0_bf[13:0] = ctx_curr_cntx_0_to_buf[13:0] ;
// buff_macro tst_mux_rep1 (width=1,dbuff=24x) (
// .dout( tcu_muxtest_rep1 ));
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_8__stack_14c__width_13 curr_cntx_1_mux (
.din0( thr0_cntx_1_q[12:0]), //
.din1( thr1_cntx_1_q[12:0]), //
.din2( thr2_cntx_1_q[12:0]), //
.din3( thr3_cntx_1_q[12:0]), //
.din4( thr4_cntx_1_q[12:0]), //
.din5( thr5_cntx_1_q[12:0]), //
.din6( thr6_cntx_1_q[12:0]), //
.din7( thr7_cntx_1_q[12:0]), //
// .muxtst (tcu_muxtest_rep1),
.sel0( ftp_itb_fetch_thr_bf[0]),
.sel1( ftp_itb_fetch_thr_bf[1]),
.sel2( ftp_itb_fetch_thr_bf[2]),
.sel3( ftp_itb_fetch_thr_bf[3]),
.sel4( ftp_itb_fetch_thr_bf[4]),
.sel5( ftp_itb_fetch_thr_bf[5]),
.sel6( ftp_itb_fetch_thr_bf[6]),
.sel7( ftp_itb_fetch_thr_bf[7]),
.dout( ctx_curr_cntx_1_to_buf[12:0] ));
ifu_ftu_ctx_dp_buff_macro__stack_14c__width_13 curr_cntx_1_buff (
.din(ctx_curr_cntx_1_to_buf[12:0]),
.dout(ctx_curr_cntx_1_bf[12:0]));
// assign ctx_curr_cntx_1_bf[12:0] = ctx_curr_cntx_1_to_buf[12:0] ;
/////////////////////////////////////////////////////////////////////
// Mux out the context to_write //
/////////////////////////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_8__stack_14c__width_14 cntx_0_to_write_mux (
.din0( thr0_cntx_0[13:0]), //
.din1( thr1_cntx_0[13:0]), //
.din2( thr2_cntx_0[13:0]), //
.din3( thr3_cntx_0[13:0]), //
.din4( thr4_cntx_0[13:0]), //
.din5( thr5_cntx_0[13:0]), //
.din6( thr6_cntx_0[13:0]), //
.din7( thr7_cntx_0[13:0]), //
.sel0( itc_thr_to_write[0]),
.sel1( itc_thr_to_write[1]),
.sel2( itc_thr_to_write[2]),
.sel3( itc_thr_to_write[3]),
.sel4( itc_thr_to_write[4]),
.sel5( itc_thr_to_write[5]),
.sel6( itc_thr_to_write[6]),
.sel7( itc_thr_to_write[7]),
.dout( ctx_cntx_0_to_write_to_buf[13:0] ));
ifu_ftu_ctx_dp_buff_macro__stack_14c__width_14 cntx_0_to_write_buf (
.din(ctx_cntx_0_to_write_to_buf[13:0]),
.dout(ctx_cntx_0_to_write_bf[13:0]));
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_8__stack_14c__width_14 cntx_1_to_write_mux (
.din0( thr0_cntx_1[13:0]), //
.din1( thr1_cntx_1[13:0]), //
.din2( thr2_cntx_1[13:0]), //
.din3( thr3_cntx_1[13:0]), //
.din4( thr4_cntx_1[13:0]), //
.din5( thr5_cntx_1[13:0]), //
.din6( thr6_cntx_1[13:0]), //
.din7( thr7_cntx_1[13:0]), //
.sel0( itc_thr_to_write[0]),
.sel1( itc_thr_to_write[1]),
.sel2( itc_thr_to_write[2]),
.sel3( itc_thr_to_write[3]),
.sel4( itc_thr_to_write[4]),
.sel5( itc_thr_to_write[5]),
.sel6( itc_thr_to_write[6]),
.sel7( itc_thr_to_write[7]),
.dout( ctx_cntx_1_to_write_to_buf[13:0] ));
ifu_ftu_ctx_dp_buff_macro__stack_14c__width_14 cntx_1_to_write_buf (
.din(ctx_cntx_1_to_write_to_buf[13:0]),
.dout(ctx_cntx_1_to_write_bf[13:0]));
// assign se = tcu_scan_en ;
assign tlu_tl_gt_0_reg_scanin = scan_in ;
assign lsu_ifu_data_reg_scanin = tlu_tl_gt_0_reg_scanout ;
assign scan_out = lsu_ifu_data_reg_scanout ;
assign thr0_cntx_0_reg_wmr_scanin = wmr_scan_in ;
assign thr0_cntx_1_reg_wmr_scanin = thr0_cntx_0_reg_wmr_scanout;
assign thr1_cntx_0_reg_wmr_scanin = thr0_cntx_1_reg_wmr_scanout;
assign thr1_cntx_1_reg_wmr_scanin = thr1_cntx_0_reg_wmr_scanout;
assign thr2_cntx_0_reg_wmr_scanin = thr1_cntx_1_reg_wmr_scanout;
assign thr2_cntx_1_reg_wmr_scanin = thr2_cntx_0_reg_wmr_scanout;
assign thr3_cntx_0_reg_wmr_scanin = thr2_cntx_1_reg_wmr_scanout;
assign thr3_cntx_1_reg_wmr_scanin = thr3_cntx_0_reg_wmr_scanout;
assign thr4_cntx_0_reg_wmr_scanin = thr3_cntx_1_reg_wmr_scanout;
assign thr4_cntx_1_reg_wmr_scanin = thr4_cntx_0_reg_wmr_scanout;
assign thr5_cntx_0_reg_wmr_scanin = thr4_cntx_1_reg_wmr_scanout;
assign thr5_cntx_1_reg_wmr_scanin = thr5_cntx_0_reg_wmr_scanout;
assign thr6_cntx_0_reg_wmr_scanin = thr5_cntx_1_reg_wmr_scanout;
assign thr6_cntx_1_reg_wmr_scanin = thr6_cntx_0_reg_wmr_scanout;
assign thr7_cntx_0_reg_wmr_scanin = thr6_cntx_1_reg_wmr_scanout;
assign thr7_cntx_1_reg_wmr_scanin = thr7_cntx_0_reg_wmr_scanout;
assign wmr_scan_out = thr7_cntx_1_reg_wmr_scanout;
module ifu_ftu_ctx_dp_buff_macro__dbuff_32x__stack_none__width_4 (
// any PARAMS parms go into naming of macro
module ifu_ftu_ctx_dp_msff_macro__stack_14c__width_8 (
module ifu_ftu_ctx_dp_buff_macro__stack_14c__width_8 (
// any PARAMS parms go into naming of macro
module ifu_ftu_ctx_dp_msff_macro__stack_14c__width_13 (
.so({so[11:0],scan_out}),
// parity macro (even parity)
module ifu_ftu_ctx_dp_prty_macro__width_16 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 (
cl_dp1_muxbuff2_8x c0_0 (
// any PARAMS parms go into naming of macro
module ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 (
.so({so[12:0],scan_out}),
// nand macro for ports = 2,3,4
module ifu_ftu_ctx_dp_nand_macro__ports_2__stack_14c__width_8 (
// and macro for ports = 2,3,4
module ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_8__stack_14c__width_13 (
cl_dp1_muxbuff8_8x c0_0 (
module ifu_ftu_ctx_dp_buff_macro__stack_14c__width_13 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_8__stack_14c__width_14 (
cl_dp1_muxbuff8_8x c0_0 (
module ifu_ftu_ctx_dp_buff_macro__stack_14c__width_14 (