// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: mmu_asd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
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// otherwise unspecified.
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// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
wire [3:0] htc_wr_itlb_tag_access;
wire [3:0] htc_wr_dtlb_tag_access;
wire [60:48] wr_data_unused;
wire [12:0] mra_wr_data_unused;
wire mra_read_1_lat_scanin;
wire mra_read_1_lat_scanout;
wire mra_read_0_lat_scanin;
wire mra_read_0_lat_scanout;
wire p_context_lat_wmr_scanin;
wire p_context_lat_wmr_scanout;
wire [12:0] p_context_0_3;
wire [12:0] p_context_0_2;
wire [12:0] p_context_0_1;
wire [12:0] p_context_0_0;
wire immu_tag_access_3_lat_wmr_scanin;
wire immu_tag_access_3_lat_wmr_scanout;
wire [47:0] immu_tag_access_3;
wire immu_tag_access_2_lat_wmr_scanin;
wire immu_tag_access_2_lat_wmr_scanout;
wire [47:0] immu_tag_access_2;
wire immu_tag_access_1_lat_wmr_scanin;
wire immu_tag_access_1_lat_wmr_scanout;
wire [47:0] immu_tag_access_1;
wire immu_tag_access_0_lat_wmr_scanin;
wire immu_tag_access_0_lat_wmr_scanout;
wire [47:0] immu_tag_access_0;
wire [61:0] immu_access_target;
wire dmmu_tag_access_3_lat_wmr_scanin;
wire dmmu_tag_access_3_lat_wmr_scanout;
wire [47:0] dmmu_tag_access_3;
wire dmmu_tag_access_2_lat_wmr_scanin;
wire dmmu_tag_access_2_lat_wmr_scanout;
wire [47:0] dmmu_tag_access_2;
wire dmmu_tag_access_1_lat_wmr_scanin;
wire dmmu_tag_access_1_lat_wmr_scanout;
wire [47:0] dmmu_tag_access_1;
wire dmmu_tag_access_0_lat_wmr_scanin;
wire dmmu_tag_access_0_lat_wmr_scanout;
wire [47:0] dmmu_tag_access_0;
wire [61:0] dmmu_access_target;
wire [2:0] tag_access_sel;
wire [48:0] itlb_data_in_0;
wire [48:0] itlb_data_in_1;
wire [48:0] itlb_data_in_2;
wire [48:0] itlb_data_in_3;
wire [50:0] dtlb_data_in_0;
wire [50:0] dtlb_data_in_1;
wire [50:0] dtlb_data_in_2;
wire [50:0] dtlb_data_in_3;
wire itlb_data_in_3_lat_scanin;
wire itlb_data_in_3_lat_scanout;
wire itlb_data_in_2_lat_scanin;
wire itlb_data_in_2_lat_scanout;
wire itlb_data_in_1_lat_scanin;
wire itlb_data_in_1_lat_scanout;
wire itlb_data_in_0_lat_scanin;
wire itlb_data_in_0_lat_scanout;
wire dtlb_data_in_3_lat_scanin;
wire dtlb_data_in_3_lat_scanout;
wire dtlb_data_in_2_lat_scanin;
wire dtlb_data_in_2_lat_scanout;
wire dtlb_data_in_1_lat_scanin;
wire dtlb_data_in_1_lat_scanout;
wire dtlb_data_in_0_lat_scanin;
wire dtlb_data_in_0_lat_scanout;
input spc_aclk_wmr; // Warm reset (non)scan
input [47:13] ase_lsu_va_w;
input [12:0] ase_lsu_context_w;
input asi_mra_rd_en_last;
input [3:0] asi_rd_immu_tag_target;
input [3:0] asi_rd_immu_tag_access;
input [3:0] asi_rd_dmmu_tag_target;
input [3:0] asi_rd_dmmu_tag_access;
input asi_rd_i_access_target;
input asi_rd_d_access_target;
input asi_rd_access_target;
input [3:0] asi_rd_itte_tag;
input [3:0] asi_rd_itte_data;
input [63:0] asi_wr_data;
input [3:0] asi_wr_immu_tag_access;
input [3:0] asi_i_tag_access_en;
input [3:0] asi_wr_itlb_data_in;
input [3:0] asi_wr_itlb_data_access;
input [3:0] asi_wr_immu_demap;
input [3:0] asi_wr_immu_demap_p;
input [3:0] asi_wr_immu_demap_n;
input [3:0] asi_i_data_in_en;
input [3:0] asi_wr_dmmu_tag_access;
input [3:0] asi_d_tag_access_en;
input [3:0] asi_wr_dtlb_data_in;
input [3:0] asi_wr_dtlb_data_access;
input [3:0] asi_wr_dmmu_demap;
input [3:0] asi_wr_dmmu_demap_p;
input [3:0] asi_wr_dmmu_demap_s_n;
input [3:0] asi_d_data_in_en;
input [3:0] asi_wr_p_context_0;
input asi_p_context_0_en;
input [2:0] asi_tag_access_sel;
input [39:0] asi_mra_wr_data;
input asi_mra_rd_addr_bit_1;
input [3:0] tlu_load_i_tag_access_p;
input [3:0] tlu_load_i_tag_access_n;
input [3:0] tlu_load_d_tag_access;
input [3:0] tlu_load_d_tag_access_r;
input [47:0] htd_tagaccess_din;
input [38:0] htd_tlbdatain_din;
input [3:0] htc_wr_itlb_data_in;
input [3:0] htc_wr_dtlb_data_in;
input mmu_use_context_0; // HW TW: Replace TTE ctxt with ctxt 0
input mmu_use_context_1; // HW TW: Replace TTE ctxt with ctxt 1
input mmu_sec_context; // HW TW: Replace TTE ctxt with secon.
output wmr_scan_out; // Warm reset (non)scan
output [81:0] asd_rd_data;
output [63:0] asd_asi_rd_data;
output [47:0] asd_dtte_tag;
output [54:0] asd_dtte_data;
output [47:0] asd_itte_tag_data_;
output [6:0] asd_itte_index;
output [12:0] asd_iht_p_ctx_0_0;
output [12:0] asd_iht_p_ctx_0_1;
output [12:0] asd_iht_p_ctx_0_2;
output [12:0] asd_iht_p_ctx_0_3;
output [47:0] asd_tag_access;
output asd_asi_zero_context;
output asd_mra_rd_addr_bit_1;
output [47:13] asd_pc_w; // Needs to feed mmu_htd_dp
//////////////////////////////////////////////////////////////////////////////
assign htc_wr_itlb_tag_access[3:0] =
htc_wr_itlb_data_in[3:0];
assign htc_wr_dtlb_tag_access[3:0] =
htc_wr_dtlb_data_in[3:0];
assign wr_data_unused[60:48] =
assign mra_wr_data_unused[12:10] =
assign mra_wr_data_unused[2:0] =
//////////////////////////////////////////////////////////////////////
mmu_asd_dp_buff_macro__width_4 clk_control_buf (
//////////////////////////////////////////////////////////////////////
// Capture read data from mra
mmu_asd_dp_msff_macro__minbuff_1__stack_58c__width_24 mra_read_1_lat (
.scan_in(mra_read_1_lat_scanin),
.scan_out(mra_read_1_lat_scanout),
.en (asi_mra_rd_en_last ),
.dout (mra_rd_data [81:58]),
mmu_asd_dp_msff_macro__minbuff_1__stack_58c__width_58 mra_read_0_lat (
.scan_in(mra_read_0_lat_scanin),
.scan_out(mra_read_0_lat_scanout),
.en (asi_mra_rd_en_last ),
.dout (mra_rd_data [57:0] ),
assign asd_rd_data[81:0] =
//////////////////////////////////////////////////////////////////////
// Shadow copy of p_context_0 for tag_access regs
mmu_asd_dp_msff_macro__mux_aonpe__ports_4__stack_58c__width_52 p_context_lat (
.scan_in(p_context_lat_wmr_scanin),
.scan_out(p_context_lat_wmr_scanout),
.din0 ({p_context_0_3 [12:0],
.din1 ({p_context_0_3 [12:0],
.din2 ({p_context_0_3 [12:0],
.din3 ({asi_wr_data [12:0],
.sel0 (asi_wr_p_context_0 [0 ] ),
.sel1 (asi_wr_p_context_0 [1 ] ),
.sel2 (asi_wr_p_context_0 [2 ] ),
.sel3 (asi_wr_p_context_0 [3 ] ),
.en (asi_p_context_0_en ),
.dout ({p_context_0_3 [12:0],
mmu_asd_dp_buff_macro__left_13__stack_58c__width_35 pc_w_buf (
.din (tlu_pc_w [47:13] ),
.dout (asd_pc_w [47:13] )
mmu_asd_dp_msff_macro__mux_aope__ports_7__stack_58c__width_48 immu_tag_access_3_lat (
.scan_in(immu_tag_access_3_lat_wmr_scanin),
.scan_out(immu_tag_access_3_lat_wmr_scanout),
.din0 ({asd_pc_w [47:13],
.din1 ({asd_pc_w [47:13],
.din2 (asi_wr_data [47:0] ),
.din3 ({asi_wr_data [47:40], // Demap VA[47:40] in data
.din4 ({asi_wr_data [47:40], // Demap VA[47:40] in data
.din5 (htd_tagaccess_din [47:0] ),
.din6 (immu_tag_access_3 [47:0] ),
.sel0 (tlu_load_i_tag_access_p[3 ] ),
.sel1 (tlu_load_i_tag_access_n[3 ] ),
.sel2 (asi_wr_immu_tag_access [3 ] ),
.sel3 (asi_wr_immu_demap_p [3 ] ),
.sel4 (asi_wr_immu_demap_n [3 ] ),
.sel5 (htc_wr_itlb_tag_access [3 ] ), // HWTW Write ITLB Tag Access
.en (asi_i_tag_access_en [3 ] ),
.dout (immu_tag_access_3 [47:0] ),
mmu_asd_dp_msff_macro__mux_aope__ports_7__stack_58c__width_48 immu_tag_access_2_lat (
.scan_in(immu_tag_access_2_lat_wmr_scanin),
.scan_out(immu_tag_access_2_lat_wmr_scanout),
.din0 ({asd_pc_w [47:13],
.din1 ({asd_pc_w [47:13],
.din2 (asi_wr_data [47:0] ),
.din3 ({asi_wr_data [47:40], // Demap VA[47:40] in data
.din4 ({asi_wr_data [47:40], // Demap VA[47:40] in data
.din5 (htd_tagaccess_din [47:0] ),
.din6 (immu_tag_access_2 [47:0] ),
.sel0 (tlu_load_i_tag_access_p[2 ] ),
.sel1 (tlu_load_i_tag_access_n[2 ] ),
.sel2 (asi_wr_immu_tag_access [2 ] ),
.sel3 (asi_wr_immu_demap_p [2 ] ),
.sel4 (asi_wr_immu_demap_n [2 ] ),
.sel5 (htc_wr_itlb_tag_access [2 ] ), // HWTW Write ITLB Tag Access
.en (asi_i_tag_access_en [2 ] ),
.dout (immu_tag_access_2 [47:0] ),
mmu_asd_dp_msff_macro__mux_aope__ports_7__stack_58c__width_48 immu_tag_access_1_lat (
.scan_in(immu_tag_access_1_lat_wmr_scanin),
.scan_out(immu_tag_access_1_lat_wmr_scanout),
.din0 ({asd_pc_w [47:13],
.din1 ({asd_pc_w [47:13],
.din2 (asi_wr_data [47:0] ),
.din3 ({asi_wr_data [47:40], // Demap VA[47:40] in data
.din4 ({asi_wr_data [47:40], // Demap VA[47:40] in data
.din5 (htd_tagaccess_din [47:0] ),
.din6 (immu_tag_access_1 [47:0] ),
.sel0 (tlu_load_i_tag_access_p[1 ] ),
.sel1 (tlu_load_i_tag_access_n[1 ] ),
.sel2 (asi_wr_immu_tag_access [1 ] ),
.sel3 (asi_wr_immu_demap_p [1 ] ),
.sel4 (asi_wr_immu_demap_n [1 ] ),
.sel5 (htc_wr_itlb_tag_access [1 ] ), // HWTW Write ITLB Tag Access
.en (asi_i_tag_access_en [1 ] ),
.dout (immu_tag_access_1 [47:0] ),
mmu_asd_dp_msff_macro__mux_aope__ports_7__stack_58c__width_48 immu_tag_access_0_lat (
.scan_in(immu_tag_access_0_lat_wmr_scanin),
.scan_out(immu_tag_access_0_lat_wmr_scanout),
.din0 ({asd_pc_w [47:13],
.din1 ({asd_pc_w [47:13],
.din2 (asi_wr_data [47:0] ),
.din3 ({asi_wr_data [47:40], // Demap VA[47:40] in data
.din4 ({asi_wr_data [47:40], // Demap VA[47:40] in data
.din5 (htd_tagaccess_din [47:0] ),
.din6 (immu_tag_access_0 [47:0] ),
.sel0 (tlu_load_i_tag_access_p[0 ] ),
.sel1 (tlu_load_i_tag_access_n[0 ] ),
.sel2 (asi_wr_immu_tag_access [0 ] ),
.sel3 (asi_wr_immu_demap_p [0 ] ),
.sel4 (asi_wr_immu_demap_n [0 ] ),
.sel5 (htc_wr_itlb_tag_access [0 ] ), // HWTW Write ITLB Tag Access
.en (asi_i_tag_access_en [0 ] ),
.dout (immu_tag_access_0 [47:0] ),
mmu_asd_dp_mux_macro__mux_aonpe__ports_8__width_62 immu_access_target_mux (
.din0 ({{14 {immu_tag_access_0[47 ]}},
immu_tag_access_0 [47:0]}),
.din1 ({{14 {immu_tag_access_1[47 ]}},
immu_tag_access_1 [47:0]}),
.din2 ({{14 {immu_tag_access_2[47 ]}},
immu_tag_access_2 [47:0]}),
.din3 ({{14 {immu_tag_access_3[47 ]}},
immu_tag_access_3 [47:0]}),
immu_tag_access_0 [12:0],
{16 {immu_tag_access_0[47 ]}},
immu_tag_access_0 [47:22]}), // tag target
immu_tag_access_1 [12:0],
{16 {immu_tag_access_1[47 ]}},
immu_tag_access_1 [47:22]}), // tag target
immu_tag_access_2 [12:0],
{16 {immu_tag_access_2[47 ]}},
immu_tag_access_2 [47:22]}), // tag target
immu_tag_access_3 [12:0],
{16 {immu_tag_access_3[47 ]}},
immu_tag_access_3 [47:22]}), // tag target
.sel0 (asi_rd_immu_tag_access [0 ] ),
.sel1 (asi_rd_immu_tag_access [1 ] ),
.sel2 (asi_rd_immu_tag_access [2 ] ),
.sel3 (asi_rd_immu_tag_access [3 ] ),
.sel4 (asi_rd_immu_tag_target [0 ] ),
.sel5 (asi_rd_immu_tag_target [1 ] ),
.sel6 (asi_rd_immu_tag_target [2 ] ),
.sel7 (asi_rd_immu_tag_target [3 ] ),
.dout (immu_access_target [61:0] )
mmu_asd_dp_msff_macro__mux_aope__ports_7__stack_58c__width_48 dmmu_tag_access_3_lat (
.scan_in(dmmu_tag_access_3_lat_wmr_scanin),
.scan_out(dmmu_tag_access_3_lat_wmr_scanout),
.din0 ({ase_lsu_va_w [47:13],
ase_lsu_context_w [12:0]}),
.din1 ({ase_lsu_va_w [47:13],
.din2 (asi_wr_data [47:0] ),
.din3 ({asi_wr_data [47:40], // Demap VA[47:40] in data
.din4 ({asi_wr_data [47:40], // Demap VA[47:40] in data
.din5 (htd_tagaccess_din [47:0] ),
.din6 (dmmu_tag_access_3 [47:0] ),
.sel0 (tlu_load_d_tag_access [3 ] ),
.sel1 (tlu_load_d_tag_access_r[3 ] ),
.sel2 (asi_wr_dmmu_tag_access [3 ] ),
.sel3 (asi_wr_dmmu_demap_p [3 ] ),
.sel4 (asi_wr_dmmu_demap_s_n [3 ] ),
.sel5 (htc_wr_dtlb_tag_access [3 ] ), //HWTW Write DTLB Tag Access
.en (asi_d_tag_access_en [3 ] ),
.dout (dmmu_tag_access_3 [47:0] ),
mmu_asd_dp_msff_macro__mux_aope__ports_7__stack_58c__width_48 dmmu_tag_access_2_lat (
.scan_in(dmmu_tag_access_2_lat_wmr_scanin),
.scan_out(dmmu_tag_access_2_lat_wmr_scanout),
.din0 ({ase_lsu_va_w [47:13],
ase_lsu_context_w [12:0]}),
.din1 ({ase_lsu_va_w [47:13],
.din2 (asi_wr_data [47:0] ),
.din3 ({asi_wr_data [47:40], // Demap VA[47:40] in data
.din4 ({asi_wr_data [47:40], // Demap VA[47:40] in data
.din5 (htd_tagaccess_din [47:0] ),
.din6 (dmmu_tag_access_2 [47:0] ),
.sel0 (tlu_load_d_tag_access [2 ] ),
.sel1 (tlu_load_d_tag_access_r[2 ] ),
.sel2 (asi_wr_dmmu_tag_access [2 ] ),
.sel3 (asi_wr_dmmu_demap_p [2 ] ),
.sel4 (asi_wr_dmmu_demap_s_n [2 ] ),
.sel5 (htc_wr_dtlb_tag_access [2 ] ), //HWTW Write DTLB Tag Access
.en (asi_d_tag_access_en [2 ] ),
.dout (dmmu_tag_access_2 [47:0] ),
mmu_asd_dp_msff_macro__mux_aope__ports_7__stack_58c__width_48 dmmu_tag_access_1_lat (
.scan_in(dmmu_tag_access_1_lat_wmr_scanin),
.scan_out(dmmu_tag_access_1_lat_wmr_scanout),
.din0 ({ase_lsu_va_w [47:13],
ase_lsu_context_w [12:0]}),
.din1 ({ase_lsu_va_w [47:13],
.din2 (asi_wr_data [47:0] ),
.din3 ({asi_wr_data [47:40], // Demap VA[47:40] in data
.din4 ({asi_wr_data [47:40], // Demap VA[47:40] in data
.din5 (htd_tagaccess_din [47:0] ),
.din6 (dmmu_tag_access_1 [47:0] ),
.sel0 (tlu_load_d_tag_access [1 ] ),
.sel1 (tlu_load_d_tag_access_r[1 ] ),
.sel2 (asi_wr_dmmu_tag_access [1 ] ),
.sel3 (asi_wr_dmmu_demap_p [1 ] ),
.sel4 (asi_wr_dmmu_demap_s_n [1 ] ),
.sel5 (htc_wr_dtlb_tag_access [1 ] ), //HWTW Write DTLB Tag Access
.en (asi_d_tag_access_en [1 ] ),
.dout (dmmu_tag_access_1 [47:0] ),
mmu_asd_dp_msff_macro__mux_aope__ports_7__stack_58c__width_48 dmmu_tag_access_0_lat (
.scan_in(dmmu_tag_access_0_lat_wmr_scanin),
.scan_out(dmmu_tag_access_0_lat_wmr_scanout),
.din0 ({ase_lsu_va_w [47:13],
ase_lsu_context_w [12:0]}),
.din1 ({ase_lsu_va_w [47:13],
.din2 (asi_wr_data [47:0] ),
.din3 ({asi_wr_data [47:40], // Demap VA[47:40] in data
.din4 ({asi_wr_data [47:40], // Demap VA[47:40] in data
.din5 (htd_tagaccess_din [47:0] ),
.din6 (dmmu_tag_access_0 [47:0] ),
.sel0 (tlu_load_d_tag_access [0 ] ),
.sel1 (tlu_load_d_tag_access_r[0 ] ),
.sel2 (asi_wr_dmmu_tag_access [0 ] ),
.sel3 (asi_wr_dmmu_demap_p [0 ] ),
.sel4 (asi_wr_dmmu_demap_s_n [0 ] ),
.sel5 (htc_wr_dtlb_tag_access [0 ] ), //HWTW Write DTLB Tag Access
.en (asi_d_tag_access_en [0 ] ),
.dout (dmmu_tag_access_0 [47:0] ),
mmu_asd_dp_mux_macro__mux_aonpe__ports_8__width_62 dmmu_access_target_mux (
.din0 ({{14 {dmmu_tag_access_0[47 ]}},
dmmu_tag_access_0 [47:0]}),
.din1 ({{14 {dmmu_tag_access_1[47 ]}},
dmmu_tag_access_1 [47:0]}),
.din2 ({{14 {dmmu_tag_access_2[47 ]}},
dmmu_tag_access_2 [47:0]}),
.din3 ({{14 {dmmu_tag_access_3[47 ]}},
dmmu_tag_access_3 [47:0]}),
dmmu_tag_access_0 [12:0],
{16 {dmmu_tag_access_0[47 ]}},
dmmu_tag_access_0 [47:22]}), // tag target
dmmu_tag_access_1 [12:0],
{16 {dmmu_tag_access_1[47 ]}},
dmmu_tag_access_1 [47:22]}), // tag target
dmmu_tag_access_2 [12:0],
{16 {dmmu_tag_access_2[47 ]}},
dmmu_tag_access_2 [47:22]}), // tag target
dmmu_tag_access_3 [12:0],
{16 {dmmu_tag_access_3[47 ]}},
dmmu_tag_access_3 [47:22]}), // tag target
.sel0 (asi_rd_dmmu_tag_access [0 ] ),
.sel1 (asi_rd_dmmu_tag_access [1 ] ),
.sel2 (asi_rd_dmmu_tag_access [2 ] ),
.sel3 (asi_rd_dmmu_tag_access [3 ] ),
.sel4 (asi_rd_dmmu_tag_target [0 ] ),
.sel5 (asi_rd_dmmu_tag_target [1 ] ),
.sel6 (asi_rd_dmmu_tag_target [2 ] ),
.sel7 (asi_rd_dmmu_tag_target [3 ] ),
.dout (dmmu_access_target [61:0] )
mmu_asd_dp_mux_macro__mux_aodec__ports_8__stack_58c__width_13 tag_access_crit_mux (
.din0 (immu_tag_access_0 [12:0] ),
.din1 (immu_tag_access_1 [12:0] ),
.din2 (immu_tag_access_2 [12:0] ),
.din3 (immu_tag_access_3 [12:0] ),
.din4 (dmmu_tag_access_0 [12:0] ),
.din5 (dmmu_tag_access_1 [12:0] ),
.din6 (dmmu_tag_access_2 [12:0] ),
.din7 (dmmu_tag_access_3 [12:0] ),
.sel (asi_tag_access_sel [2:0] ),
.dout (tag_access [12:0] )
mmu_asd_dp_buff_macro__stack_58c__width_3 tag_access_sel_buf (
.din (asi_tag_access_sel [2:0] ),
.dout (tag_access_sel [2:0] )
mmu_asd_dp_mux_macro__left_13__mux_aodec__ports_8__stack_58c__width_35 tag_access_mux (
.din0 (immu_tag_access_0 [47:13] ),
.din1 (immu_tag_access_1 [47:13] ),
.din2 (immu_tag_access_2 [47:13] ),
.din3 (immu_tag_access_3 [47:13] ),
.din4 (dmmu_tag_access_0 [47:13] ),
.din5 (dmmu_tag_access_1 [47:13] ),
.din6 (dmmu_tag_access_2 [47:13] ),
.din7 (dmmu_tag_access_3 [47:13] ),
.sel (tag_access_sel [2:0] ),
.dout (tag_access [47:13] )
mmu_asd_dp_buff_macro__rep_1__stack_58c__width_48 tag_access_buf (
.din (tag_access [47:0] ),
.dout (asd_tag_access [47:0] )
mmu_asd_dp_zero_macro__width_16 zero_context_cmp (
mmu_asd_dp_nor_macro__ports_2__width_1 bit1_nor (
.din1 (asi_rd_tsb_ptr_ ),
mmu_asd_dp_or_macro__ports_2__width_1 bit1_or (
.din1 (asi_mra_rd_addr_bit_1 ),
.dout (asd_mra_rd_addr_bit_1 )
mmu_asd_dp_buff_macro__rep_1__width_2 zero_context_buf (
.din ({2 {zero_context }}),
.dout ({asd_zero_context ,
mmu_asd_dp_msff_macro__mux_aonpe__ports_2__width_62 asi_rd_mux (
.scan_in(asi_rd_mux_scanin),
.scan_out(asi_rd_mux_scanout),
.din0 (immu_access_target [61:0] ),
.din1 (dmmu_access_target [61:0] ),
.sel0 (asi_rd_i_access_target ),
.sel1 (asi_rd_d_access_target ),
.en (asi_rd_access_target ),
.dout (asd_asi_rd_data [61:0] ),
assign asd_asi_rd_data[63:62] =
{2 {asd_asi_rd_data[61]}};
mmu_asd_dp_and_macro__ports_2__stack_58c__width_8 ps_eq_256m_and (
.din0 ({itlb_data_in_0 [2 ],
.din1 ({itlb_data_in_0 [0 ],
.dout ({itlb_ps_eq_256m_0 ,
mmu_asd_dp_or_macro__ports_2__stack_58c__width_8 ps_gt_64k_or (
.din0 ({itlb_data_in_0 [2 ],
.din1 ({itlb_data_in_0 [1 ],
.dout ({itlb_ps_gt_64k_0 ,
mmu_asd_dp_or_macro__ports_3__stack_58c__width_8 ps_gt_8k_or (
.din0 ({itlb_data_in_0 [2 ],
.din1 ({itlb_data_in_0 [1 ],
.din2 ({itlb_data_in_0 [0 ],
.dout ({itlb_ps_gt_8k_0 ,
mmu_asd_dp_mux_macro__mux_aonpe__ports_4__stack_58c__width_48 itte_tag_mux (
.din0 ({immu_tag_access_0 [47:28], // VA[47:28]
immu_tag_access_0 [27:22], // VA[27:22]
itlb_data_in_0 [38 ], // Valid
itlb_data_in_0 [35 ], // Locked
immu_tag_access_0 [21:16], // VA[21:16]
immu_tag_access_0 [12:0]}), // Context
.din1 ({immu_tag_access_1 [47:28], // VA[47:28]
immu_tag_access_1 [27:22], // VA[27:22]
itlb_data_in_1 [38 ], // Valid
itlb_data_in_1 [35 ], // Locked
immu_tag_access_1 [21:16], // VA[21:16]
immu_tag_access_1 [12:0]}), // Context
.din2 ({immu_tag_access_2 [47:28], // VA[47:28]
immu_tag_access_2 [27:22], // VA[27:22]
itlb_data_in_2 [38 ], // Valid
itlb_data_in_2 [35 ], // Locked
immu_tag_access_2 [21:16], // VA[21:16]
immu_tag_access_2 [12:0]}), // Context
.din3 ({immu_tag_access_3 [47:28], // VA[47:28]
immu_tag_access_3 [27:22], // VA[27:22]
itlb_data_in_3 [38 ], // Valid
itlb_data_in_3 [35 ], // Locked
immu_tag_access_3 [21:16], // VA[21:16]
immu_tag_access_3 [12:0]}), // Context
.sel0 (asi_rd_itte_tag [0 ] ),
.sel1 (asi_rd_itte_tag [1 ] ),
.sel2 (asi_rd_itte_tag [2 ] ),
.sel3 (asi_rd_itte_tag [3 ] ),
mmu_asd_dp_mux_macro__dmux_8x__mux_aope__ports_4__stack_58c__width_48 dtte_tag_mux (
.din0 ({dmmu_tag_access_0 [47:28], // VA[47:28]
dmmu_tag_access_0 [27:22], // VA[27:22]
dtlb_data_in_0 [38 ], // Valid
dtlb_data_in_0 [35 ], // Locked
dmmu_tag_access_0 [21:16], // VA[21:16]
dmmu_tag_access_0 [12:0]}), // Context
.din1 ({dmmu_tag_access_1 [47:28], // VA[47:28]
dmmu_tag_access_1 [27:22], // VA[27:22]
dtlb_data_in_1 [38 ], // Valid
dtlb_data_in_1 [35 ], // Locked
dmmu_tag_access_1 [21:16], // VA[21:16]
dmmu_tag_access_1 [12:0]}), // Context
.din2 ({dmmu_tag_access_2 [47:28], // VA[47:28]
dmmu_tag_access_2 [27:22], // VA[27:22]
dtlb_data_in_2 [38 ], // Valid
dtlb_data_in_2 [35 ], // Locked
dmmu_tag_access_2 [21:16], // VA[21:16]
dmmu_tag_access_2 [12:0]}), // Context
.din3 ({dmmu_tag_access_3 [47:28], // VA[47:28]
dmmu_tag_access_3 [27:22], // VA[27:22]
dtlb_data_in_3 [38 ], // Valid
dtlb_data_in_3 [35 ], // Locked
dmmu_tag_access_3 [21:16], // VA[21:16]
dmmu_tag_access_3 [12:0]}), // Context
.sel0 (asi_rd_dtte [0 ] ),
.sel1 (asi_rd_dtte [1 ] ),
.sel2 (asi_rd_dtte [2 ] ),
mmu_asd_dp_buff_macro__rep_1__stack_58c__width_48 dtte_tag_buf (
.dout (asd_dtte_tag [47:0] )
asi_wr_data [62 ], // NFO
asi_data_in_real , // Real
asi_wr_data [61 ], // Locked
asi_wr_data [39:13], // PA[39:13]
asi_wr_data [11 ], // Side effect
asi_wr_data [2:0]}; // Size
mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_49 itlb_data_in_3_lat (
.scan_in(itlb_data_in_3_lat_scanin),
.scan_out(itlb_data_in_3_lat_scanout),
.din0 ({{7 {1'b0}} , // Index valid & index
{3 {1'b0}} , // Demap valid & type
.din1 ({1'b1 , // Index valid
asi_mra_wr_data [8:3], // Index to write
{3 {1'b0}} , // Demap valid & type
.din2 ({{7 {1'b0}} , // Index valid & index
asi_mra_wr_data [7:6], // Demap type field
asi_demap_r_bit , // Demap R bit
.din3 ({{7 {1'b0}} , // Index valid & index
mmu_use_context_1 , // Context type
mmu_use_context_0 , // Context type
htd_tlbdatain_din [38:0]}),
.din4 (itlb_data_in_3 [48:0] ),
.sel0 (asi_wr_itlb_data_in [3 ] ), // ASI Write
.sel1 (asi_wr_itlb_data_access[3 ] ), // ASI Write
.sel2 (asi_wr_immu_demap [3 ] ),
.sel3 (htc_wr_itlb_data_in [3 ] ), // HWTW Write ITLB Data-In
.en (asi_i_data_in_en [3 ] ),
.dout (itlb_data_in_3 [48:0] ),
mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_49 itlb_data_in_2_lat (
.scan_in(itlb_data_in_2_lat_scanin),
.scan_out(itlb_data_in_2_lat_scanout),
.din0 ({{7 {1'b0}} , // Index valid & index
{3 {1'b0}} , // Demap valid & type
.din1 ({1'b1 , // Index valid
asi_mra_wr_data [8:3], // Index to write
{3 {1'b0}} , // Demap valid & type
.din2 ({{7 {1'b0}} , // Index valid & index
asi_mra_wr_data [7:6], // Demap type field
asi_demap_r_bit , // Demap R bit
.din3 ({{7 {1'b0}} , // Index valid & index
mmu_use_context_1 , // Context type
mmu_use_context_0 , // Context type
htd_tlbdatain_din [38:0]}),
.din4 (itlb_data_in_2 [48:0] ),
.sel0 (asi_wr_itlb_data_in [2 ] ), // ASI Write
.sel1 (asi_wr_itlb_data_access[2 ] ), // ASI Write
.sel2 (asi_wr_immu_demap [2 ] ),
.sel3 (htc_wr_itlb_data_in [2 ] ), // HWTW Write ITLB Data-In
.en (asi_i_data_in_en [2 ] ),
.dout (itlb_data_in_2 [48:0] ),
mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_49 itlb_data_in_1_lat (
.scan_in(itlb_data_in_1_lat_scanin),
.scan_out(itlb_data_in_1_lat_scanout),
.din0 ({{7 {1'b0}} , // Index valid & index
{3 {1'b0}} , // Demap valid & type
.din1 ({1'b1 , // Index valid
asi_mra_wr_data [8:3], // Index to write
{3 {1'b0}} , // Demap valid & type
.din2 ({{7 {1'b0}} , // Index valid & index
asi_mra_wr_data [7:6], // Demap type field
asi_demap_r_bit , // Demap R bit
.din3 ({{7 {1'b0}} , // Index valid & index
mmu_use_context_1 , // Context type
mmu_use_context_0 , // Context type
htd_tlbdatain_din [38:0]}),
.din4 (itlb_data_in_1 [48:0] ),
.sel0 (asi_wr_itlb_data_in [1 ] ), // ASI Write
.sel1 (asi_wr_itlb_data_access[1 ] ), // ASI Write
.sel2 (asi_wr_immu_demap [1 ] ),
.sel3 (htc_wr_itlb_data_in [1 ] ), // HWTW Write ITLB Data-In
.en (asi_i_data_in_en [1 ] ),
.dout (itlb_data_in_1 [48:0] ),
mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_49 itlb_data_in_0_lat (
.scan_in(itlb_data_in_0_lat_scanin),
.scan_out(itlb_data_in_0_lat_scanout),
.din0 ({{7 {1'b0}} , // Index valid & index
{3 {1'b0}} , // Demap valid & type
.din1 ({1'b1 , // Index valid
asi_mra_wr_data [8:3], // Index to write
{3 {1'b0}} , // Demap valid & type
.din2 ({{7 {1'b0}} , // Index valid & index
asi_mra_wr_data [7:6], // Demap type field
asi_demap_r_bit , // Demap R bit
.din3 ({{7 {1'b0}} , // Index valid & index
mmu_use_context_1 , // Context type
mmu_use_context_0 , // Context type
htd_tlbdatain_din [38:0]}),
.din4 (itlb_data_in_0 [48:0] ),
.sel0 (asi_wr_itlb_data_in [0 ] ), // ASI Write
.sel1 (asi_wr_itlb_data_access[0 ] ), // ASI Write
.sel2 (asi_wr_immu_demap [0 ] ),
.sel3 (htc_wr_itlb_data_in [0 ] ), // HWTW Write ITLB Data-In
.en (asi_i_data_in_en [0 ] ),
.dout (itlb_data_in_0 [48:0] ),
mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_51 dtlb_data_in_3_lat (
.scan_in(dtlb_data_in_3_lat_scanin),
.scan_out(dtlb_data_in_3_lat_scanout),
.din0 ({{8 {1'b0}} , // Index valid & index
{4 {1'b0}} , // Demap valids & type
.din1 ({1'b1 , // Index valid
asi_mra_wr_data [9:3], // Index to write
{4 {1'b0}} , // Demap valids & type
.din2 ({{8 {1'b0}} , // Index valid & index
asi_dmmu_demap_s , // Demap secondary context
asi_mra_wr_data [7:6], // Demap type field
asi_demap_r_bit , // Demap R bit
.din3 ({{8 {1'b0}} , // Index valid & index
mmu_sec_context , // Replace with secondary cxt
mmu_use_context_1 , // Context type
mmu_use_context_0 , // Context type
htd_tlbdatain_din [38:0]}),
.din4 (dtlb_data_in_3 [50:0] ),
.sel0 (asi_wr_dtlb_data_in [3 ] ), // ASI Write
.sel1 (asi_wr_dtlb_data_access[3 ] ), // ASI Write
.sel2 (asi_wr_dmmu_demap [3 ] ),
.sel3 (htc_wr_dtlb_data_in [3 ] ), // HWTW Write DTLB Data-In
.en (asi_d_data_in_en [3 ] ),
.dout (dtlb_data_in_3 [50:0] ),
mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_51 dtlb_data_in_2_lat (
.scan_in(dtlb_data_in_2_lat_scanin),
.scan_out(dtlb_data_in_2_lat_scanout),
.din0 ({{8 {1'b0}} , // Index valid & index
{4 {1'b0}} , // Demap valids & type
.din1 ({1'b1 , // Index valid
asi_mra_wr_data [9:3], // Index to write
{4 {1'b0}} , // Demap valids & type
.din2 ({{8 {1'b0}} , // Index valid & index
asi_dmmu_demap_s , // Demap secondary context
asi_mra_wr_data [7:6], // Demap type field
asi_demap_r_bit , // Demap R bit
.din3 ({{8 {1'b0}} , // Index valid & index
mmu_sec_context , // Replace with secondary cxt
mmu_use_context_1 , // Context type
mmu_use_context_0 , // Context type
htd_tlbdatain_din [38:0]}),
.din4 (dtlb_data_in_2 [50:0] ),
.sel0 (asi_wr_dtlb_data_in [2 ] ), // ASI Write
.sel1 (asi_wr_dtlb_data_access[2 ] ), // ASI Write
.sel2 (asi_wr_dmmu_demap [2 ] ),
.sel3 (htc_wr_dtlb_data_in [2 ] ), // HWTW Write DTLB Data-In
.en (asi_d_data_in_en [2 ] ),
.dout (dtlb_data_in_2 [50:0] ),
mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_51 dtlb_data_in_1_lat (
.scan_in(dtlb_data_in_1_lat_scanin),
.scan_out(dtlb_data_in_1_lat_scanout),
.din0 ({{8 {1'b0}} , // Index valid & index
{4 {1'b0}} , // Demap valids & type
.din1 ({1'b1 , // Index valid
asi_mra_wr_data [9:3], // Index to write
{4 {1'b0}} , // Demap valids & type
.din2 ({{8 {1'b0}} , // Index valid & index
asi_dmmu_demap_s , // Demap secondary context
asi_mra_wr_data [7:6], // Demap type field
asi_demap_r_bit , // Demap R bit
.din3 ({{8 {1'b0}} , // Index valid & index
mmu_sec_context , // Replace with secondary cxt
mmu_use_context_1 , // Context type
mmu_use_context_0 , // Context type
htd_tlbdatain_din [38:0]}),
.din4 (dtlb_data_in_1 [50:0] ),
.sel0 (asi_wr_dtlb_data_in [1 ] ), // ASI Write
.sel1 (asi_wr_dtlb_data_access[1 ] ), // ASI Write
.sel2 (asi_wr_dmmu_demap [1 ] ),
.sel3 (htc_wr_dtlb_data_in [1 ] ), // HWTW Write DTLB Data-In
.en (asi_d_data_in_en [1 ] ),
.dout (dtlb_data_in_1 [50:0] ),
mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_51 dtlb_data_in_0_lat (
.scan_in(dtlb_data_in_0_lat_scanin),
.scan_out(dtlb_data_in_0_lat_scanout),
.din0 ({{8 {1'b0}} , // Index valid & index
{4 {1'b0}} , // Demap valids & type
.din1 ({1'b1 , // Index valid
asi_mra_wr_data [9:3], // Index to write
{4 {1'b0}} , // Demap valids & type
.din2 ({{8 {1'b0}} , // Index valid & index
asi_dmmu_demap_s , // Demap secondary context
asi_mra_wr_data [7:6], // Demap type field
asi_demap_r_bit , // Demap R bit
.din3 ({{8 {1'b0}} , // Index valid & index
mmu_sec_context , // Replace with secondary cxt
mmu_use_context_1 , // Context type
mmu_use_context_0 , // Context type
htd_tlbdatain_din [38:0]}),
.din4 (dtlb_data_in_0 [50:0] ),
.sel0 (asi_wr_dtlb_data_in [0 ] ), // ASI Write
.sel1 (asi_wr_dtlb_data_access[0 ] ),
.sel2 (asi_wr_dmmu_demap [0 ] ),
.sel3 (htc_wr_dtlb_data_in [0 ] ), // HWTW Write DTLB Data-In
.en (asi_d_data_in_en [0 ] ),
.dout (dtlb_data_in_0 [50:0] ),
mmu_asd_dp_mux_macro__dmux_8x__mux_aonpe__ports_4__stack_58c__width_53 itte_data_mux (
.din0 ({itlb_data_in_0 [48:39], // Demap info, etc.
immu_tag_access_0 [15:13], // VA[15:13]
thread_group , // TID[02]
itlb_data_in_0 [36 ], // Real bit
itlb_data_in_0 [34:23], // PA[39:28]
itlb_data_in_0 [22:17], // PA[27:22]
itlb_data_in_0 [16:11], // PA[21:16]
itlb_data_in_0 [10:8], // PA[15:13]
itlb_data_in_0 [38 ], // Valid
itlb_data_in_0 [37 ], // NFO
itlb_data_in_0 [7 ], // IE
itlb_data_in_0 [5 ], // CP
itlb_data_in_0 [6 ], // E
itlb_data_in_0 [4 ], // P
itlb_data_in_0 [3 ]}), // W
.din1 ({itlb_data_in_1 [48:39], // Demap info, etc.
immu_tag_access_1 [15:13], // VA[15:13]
thread_group , // TID[02]
itlb_data_in_1 [36 ], // Real bit
itlb_data_in_1 [34:23], // PA[39:28]
itlb_data_in_1 [22:17], // PA[27:22]
itlb_data_in_1 [16:11], // PA[21:16]
itlb_data_in_1 [10:8], // PA[15:13]
itlb_data_in_1 [38 ], // Valid
itlb_data_in_1 [37 ], // NFO
itlb_data_in_1 [7 ], // IE
itlb_data_in_1 [5 ], // CP
itlb_data_in_1 [6 ], // E
itlb_data_in_1 [4 ], // P
itlb_data_in_1 [3 ]}), // W
.din2 ({itlb_data_in_2 [48:39], // Demap info, etc.
immu_tag_access_2 [15:13], // VA[15:13]
thread_group , // TID[02]
itlb_data_in_2 [36 ], // Real bit
itlb_data_in_2 [34:23], // PA[39:28]
itlb_data_in_2 [22:17], // PA[27:22]
itlb_data_in_2 [16:11], // PA[21:16]
itlb_data_in_2 [10:8], // PA[15:13]
itlb_data_in_2 [38 ], // Valid
itlb_data_in_2 [37 ], // NFO
itlb_data_in_2 [7 ], // IE
itlb_data_in_2 [5 ], // CP
itlb_data_in_2 [6 ], // E
itlb_data_in_2 [4 ], // P
itlb_data_in_2 [3 ]}), // W
.din3 ({itlb_data_in_3 [48:39], // Demap info, etc.
immu_tag_access_3 [15:13], // VA[15:13]
thread_group , // TID[02]
itlb_data_in_3 [36 ], // Real bit
itlb_data_in_3 [34:23], // PA[39:28]
itlb_data_in_3 [22:17], // PA[27:22]
itlb_data_in_3 [16:11], // PA[21:16]
itlb_data_in_3 [10:8], // PA[15:13]
itlb_data_in_3 [38 ], // Valid
itlb_data_in_3 [37 ], // NFO
itlb_data_in_3 [7 ], // IE
itlb_data_in_3 [5 ], // CP
itlb_data_in_3 [6 ], // E
itlb_data_in_3 [4 ], // P
itlb_data_in_3 [3 ]}), // W
.sel0 (asi_rd_itte_data [0 ] ),
.sel1 (asi_rd_itte_data [1 ] ),
.sel2 (asi_rd_itte_data [2 ] ),
.sel3 (asi_rd_itte_data [3 ] ),
.dout ({asd_itte_index [6:0],
// Merge ITLB tag and data
mmu_asd_dp_nor_macro__ports_2__stack_58c__width_48 itte_tag_data_b_nor (
.din0 (itte_tag [47:0] ),
.dout (asd_itte_tag_data_ [47:0] )
mmu_asd_dp_mux_macro__mux_aope__ports_4__stack_58c__width_55 dtte_data_mux (
.din0 ({dtlb_data_in_0 [50:39], // Demap info, etc
dmmu_tag_access_0 [15:13], // VA[15:13]
thread_group , // TID[02]
dtlb_data_in_0 [36 ], // Real bit
dtlb_data_in_0 [34:23], // PA[39:28]
dtlb_data_in_0 [22:17], // PA[27:22]
dtlb_data_in_0 [16:11], // PA[21:16]
dtlb_data_in_0 [10:8], // PA[15:13]
dtlb_data_in_0 [38 ], // Valid
dtlb_data_in_0 [37 ], // NFO
dtlb_data_in_0 [7 ], // IE
dtlb_data_in_0 [5 ], // CP
dtlb_data_in_0 [6 ], // E (Side effect)
dtlb_data_in_0 [4 ], // P
dtlb_data_in_0 [3 ]}), // W
.din1 ({dtlb_data_in_1 [50:39], // Demap info, etc
dmmu_tag_access_1 [15:13], // VA[15:13]
thread_group , // TID[02]
dtlb_data_in_1 [36 ], // Real bit
dtlb_data_in_1 [34:23], // PA[39:28]
dtlb_data_in_1 [22:17], // PA[27:22]
dtlb_data_in_1 [16:11], // PA[21:16]
dtlb_data_in_1 [10:8], // PA[15:13]
dtlb_data_in_1 [38 ], // Valid
dtlb_data_in_1 [37 ], // NFO
dtlb_data_in_1 [7 ], // IE
dtlb_data_in_1 [5 ], // CP
dtlb_data_in_1 [6 ], // E (Side effect)
dtlb_data_in_1 [4 ], // P
dtlb_data_in_1 [3 ]}), // W
.din2 ({dtlb_data_in_2 [50:39], // Demap info, etc
dmmu_tag_access_2 [15:13], // VA[15:13]
thread_group , // TID[02]
dtlb_data_in_2 [36 ], // Real bit
dtlb_data_in_2 [34:23], // PA[39:28]
dtlb_data_in_2 [22:17], // PA[27:22]
dtlb_data_in_2 [16:11], // PA[21:16]
dtlb_data_in_2 [10:8], // PA[15:13]
dtlb_data_in_2 [38 ], // Valid
dtlb_data_in_2 [37 ], // NFO
dtlb_data_in_2 [7 ], // IE
dtlb_data_in_2 [5 ], // CP
dtlb_data_in_2 [6 ], // E (Side effect)
dtlb_data_in_2 [4 ], // P
dtlb_data_in_2 [3 ]}), // W
.din3 ({dtlb_data_in_3 [50:39], // Demap info, etc
dmmu_tag_access_3 [15:13], // VA[15:13]
thread_group , // TID[02]
dtlb_data_in_3 [36 ], // Real bit
dtlb_data_in_3 [34:23], // PA[39:28]
dtlb_data_in_3 [22:17], // PA[27:22]
dtlb_data_in_3 [16:11], // PA[21:16]
dtlb_data_in_3 [10:8], // PA[15:13]
dtlb_data_in_3 [38 ], // Valid
dtlb_data_in_3 [37 ], // NFO
dtlb_data_in_3 [7 ], // IE
dtlb_data_in_3 [5 ], // CP
dtlb_data_in_3 [6 ], // E (Side effect)
dtlb_data_in_3 [4 ], // P
dtlb_data_in_3 [3 ]}), // W
.sel0 (asi_rd_dtte [0 ] ),
.sel1 (asi_rd_dtte [1 ] ),
.sel2 (asi_rd_dtte [2 ] ),
.dout (dtte_data [54:0] )
mmu_asd_dp_buff_macro__rep_1__stack_58c__width_55 dtte_data_buf (
.din (dtte_data [54:0] ),
.dout (asd_dtte_data [54:0] )
assign asd_iht_p_ctx_0_0 [12:0] = p_context_0_0 [12:0];
assign asd_iht_p_ctx_0_1 [12:0] = p_context_0_1 [12:0];
assign asd_iht_p_ctx_0_2 [12:0] = p_context_0_2 [12:0];
assign asd_iht_p_ctx_0_3 [12:0] = p_context_0_3 [12:0];
//////////////////////////////////////////////////////////////////////
assign mra_read_1_lat_scanin = scan_in ;
assign mra_read_0_lat_scanin = mra_read_1_lat_scanout ;
assign asi_rd_mux_scanin = mra_read_0_lat_scanout ;
assign itlb_data_in_3_lat_scanin = asi_rd_mux_scanout ;
assign itlb_data_in_2_lat_scanin = itlb_data_in_3_lat_scanout;
assign itlb_data_in_1_lat_scanin = itlb_data_in_2_lat_scanout;
assign itlb_data_in_0_lat_scanin = itlb_data_in_1_lat_scanout;
assign dtlb_data_in_3_lat_scanin = itlb_data_in_0_lat_scanout;
assign dtlb_data_in_2_lat_scanin = dtlb_data_in_3_lat_scanout;
assign dtlb_data_in_1_lat_scanin = dtlb_data_in_2_lat_scanout;
assign dtlb_data_in_0_lat_scanin = dtlb_data_in_1_lat_scanout;
assign scan_out = dtlb_data_in_0_lat_scanout;
assign p_context_lat_wmr_scanin = wmr_scan_in ;
assign immu_tag_access_3_lat_wmr_scanin = p_context_lat_wmr_scanout;
assign immu_tag_access_2_lat_wmr_scanin = immu_tag_access_3_lat_wmr_scanout;
assign immu_tag_access_1_lat_wmr_scanin = immu_tag_access_2_lat_wmr_scanout;
assign immu_tag_access_0_lat_wmr_scanin = immu_tag_access_1_lat_wmr_scanout;
assign dmmu_tag_access_3_lat_wmr_scanin = immu_tag_access_0_lat_wmr_scanout;
assign dmmu_tag_access_2_lat_wmr_scanin = dmmu_tag_access_3_lat_wmr_scanout;
assign dmmu_tag_access_1_lat_wmr_scanin = dmmu_tag_access_2_lat_wmr_scanout;
assign dmmu_tag_access_0_lat_wmr_scanin = dmmu_tag_access_1_lat_wmr_scanout;
assign wmr_scan_out = dmmu_tag_access_0_lat_wmr_scanout;
module mmu_asd_dp_buff_macro__width_4 (
// any PARAMS parms go into naming of macro
module mmu_asd_dp_msff_macro__minbuff_1__stack_58c__width_24 (
.so({so[22:0],scan_out}),
// any PARAMS parms go into naming of macro
module mmu_asd_dp_msff_macro__minbuff_1__stack_58c__width_58 (
.so({so[56:0],scan_out}),
// any PARAMS parms go into naming of macro
module mmu_asd_dp_msff_macro__mux_aonpe__ports_4__stack_58c__width_52 (
cl_dp1_muxbuff4_8x c1_0 (
.so({so[50:0],scan_out}),
module mmu_asd_dp_buff_macro__left_13__stack_58c__width_35 (
// any PARAMS parms go into naming of macro
module mmu_asd_dp_msff_macro__mux_aope__ports_7__stack_58c__width_48 (
.so({so[46:0],scan_out}),
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module mmu_asd_dp_mux_macro__mux_aonpe__ports_8__width_62 (
cl_dp1_muxbuff8_8x c0_0 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module mmu_asd_dp_mux_macro__mux_aodec__ports_8__stack_58c__width_13 (
module mmu_asd_dp_buff_macro__stack_58c__width_3 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module mmu_asd_dp_mux_macro__left_13__mux_aodec__ports_8__stack_58c__width_35 (
module mmu_asd_dp_buff_macro__rep_1__stack_58c__width_48 (
// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
module mmu_asd_dp_zero_macro__width_16 (
// nor macro for ports = 2,3
module mmu_asd_dp_nor_macro__ports_2__width_1 (
// or macro for ports = 2,3
module mmu_asd_dp_or_macro__ports_2__width_1 (
module mmu_asd_dp_buff_macro__rep_1__width_2 (
// any PARAMS parms go into naming of macro
module mmu_asd_dp_msff_macro__mux_aonpe__ports_2__width_62 (
cl_dp1_muxbuff2_8x c1_0 (
.so({so[60:0],scan_out}),
// and macro for ports = 2,3,4
module mmu_asd_dp_and_macro__ports_2__stack_58c__width_8 (
// or macro for ports = 2,3
module mmu_asd_dp_or_macro__ports_2__stack_58c__width_8 (
// or macro for ports = 2,3
module mmu_asd_dp_or_macro__ports_3__stack_58c__width_8 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module mmu_asd_dp_mux_macro__mux_aonpe__ports_4__stack_58c__width_48 (
cl_dp1_muxbuff4_8x c0_0 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module mmu_asd_dp_mux_macro__dmux_8x__mux_aope__ports_4__stack_58c__width_48 (
// any PARAMS parms go into naming of macro
module mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_49 (
.so({so[47:0],scan_out}),
// any PARAMS parms go into naming of macro
module mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_51 (
.so({so[49:0],scan_out}),
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module mmu_asd_dp_mux_macro__dmux_8x__mux_aonpe__ports_4__stack_58c__width_53 (
cl_dp1_muxbuff4_8x c0_0 (
// nor macro for ports = 2,3
module mmu_asd_dp_nor_macro__ports_2__stack_58c__width_48 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module mmu_asd_dp_mux_macro__mux_aope__ports_4__stack_58c__width_55 (
module mmu_asd_dp_buff_macro__rep_1__stack_58c__width_55 (