design/sys/iop/spc/spc_rtl.flist

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: spc_rtl.flist
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// have any questions.
//
// ========== Copyright Header End ============================================
$DV_ROOT/design/sys/iop/spc/rtl/spc.v
-v $DV_ROOT/design/sys/iop/spc/rtl/dmo_dp.v
-v $DV_ROOT/design/sys/iop/spc/rtl/spc_lb_ctl.v
-v $DV_ROOT/design/sys/iop/spc/rtl/spc_mb0_ctl.v
-v $DV_ROOT/design/sys/iop/spc/rtl/spc_mb1_ctl.v
-v $DV_ROOT/design/sys/iop/spc/rtl/spc_mb2_ctl.v
-v $DV_ROOT/design/sys/iop/spc/rtl/spc_msf0_dp.v
-v $DV_ROOT/design/sys/iop/spc/rtl/spc_msf1_dp.v
-v $DV_ROOT/design/sys/iop/spc/rtl/spc_rep1_dp.v
$DV_ROOT/design/sys/iop/spc/dec/rtl/dec.v
-v $DV_ROOT/design/sys/iop/spc/dec/rtl/dec_dcd_ctl.v
-v $DV_ROOT/design/sys/iop/spc/dec/rtl/dec_ded_ctl.v
-v $DV_ROOT/design/sys/iop/spc/dec/rtl/dec_del_ctl.v
$DV_ROOT/design/sys/iop/spc/exu/rtl/exu.v
-v $DV_ROOT/design/sys/iop/spc/exu/rtl/exu_ecc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/exu/rtl/exu_ect_ctl.v
-v $DV_ROOT/design/sys/iop/spc/exu/rtl/exu_edp_dp.v
-v $DV_ROOT/design/sys/iop/spc/exu/rtl/exu_mdp_dp.v
-v $DV_ROOT/design/sys/iop/spc/exu/rtl/exu_rml_ctl.v
$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu.v
-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fac_ctl.v
-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fad_dp.v
-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fdc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fdd_dp.v
-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fec_ctl.v
-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fgd_dp.v
-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fic_ctl.v
-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fpc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fpe_dp.v
-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fpf_dp.v
-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fpy_dp.v
-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_rep_dp.v
$DV_ROOT/design/sys/iop/spc/gkt/rtl/gkt.v
-v $DV_ROOT/design/sys/iop/spc/gkt/rtl/gkt_ipc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/gkt/rtl/gkt_ipd_dp.v
-v $DV_ROOT/design/sys/iop/spc/gkt/rtl/gkt_leg_ctl.v
-v $DV_ROOT/design/sys/iop/spc/gkt/rtl/gkt_pqm_ctl.v
$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_cmt_ctl.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_csm_ctl.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_lsi_ctl.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_lsi_dp.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_msb_ctl.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_msb_dp.v
$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_agc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_agd_dp.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_asi_ctl.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_byp_dp.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_cms_ctl.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_ctx_dp.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_err_dp.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_ftp_ctl.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_itc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_itd_dp.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_red_ctl.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_tfc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_tsm_ctl.v
$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ibu.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ibu_ibf_dp.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ibu_ibq_ctl.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_adc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_arc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_ard_dp.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_asc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_asd_dp.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_cic_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_cid_dp.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_dac_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_dcc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_dcd_dp.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_dcp_dp.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_dcs_dp.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_lmc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_lmd_dp.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_lru8_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_pic_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_pid_dp.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_red_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_rep_dp.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_sbc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_sbd_dp.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_sbs_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_sec_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_sed_dp.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_spd_dp.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_tgc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_tgd_dp.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_tlc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_tld_dp.v
$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_asd_dp.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_ase_dp.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_asi_ctl.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_eem_dp.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_htc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_htd_dp.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_mbd_dp.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_mec_dp.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_mel_dp.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_mem_dp.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_sed_dp.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_seg_dp.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_sel_dp.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_tmc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_trc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_trs_ctl.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_tsm_ctl.v
$DV_ROOT/design/sys/iop/spc/pku/rtl/pku.v
-v $DV_ROOT/design/sys/iop/spc/pku/rtl/pku_pck_ctl.v
-v $DV_ROOT/design/sys/iop/spc/pku/rtl/pku_pkd_dp.v
-v $DV_ROOT/design/sys/iop/spc/pku/rtl/pku_swl_ctl.v
-v $DV_ROOT/design/sys/iop/spc/pmu/rtl/pmu.v
-v $DV_ROOT/design/sys/iop/spc/pmu/rtl/pmu_pct_ctl.v
-v $DV_ROOT/design/sys/iop/spc/pmu/rtl/pmu_pdp_dp.v
$DV_ROOT/design/sys/iop/spc/spu/rtl/spu.v
$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_asi_ctl.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_cel_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_cep_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_cer_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_cth_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_cxi_ctl.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_dfd_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_ecd_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_ecg_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_eem_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_fls_ctl.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_mbd_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_npc_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_pct_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_ras_ctl.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_ssd_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_sse_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_tel_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_tic_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_trl_ctl.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_tsb_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_tsd_dp.v