design/sys/iop/tds/synopsys/script/user_cfg.scr

source -echo -verbose $dv_root/design/sys/synopsys/script/project_io_cfg.scr

set rtl_files {\
libs/cl/cl_rtl_ext.v
libs/cl/cl_a1/cl_a1.behV
libs/cl/cl_u1/cl_u1.behV
libs/cl/cl_dp1/cl_dp1.behV
libs/cl/cl_sc1/cl_sc1.behV
libs/cl/cl_mc1/cl_mc1.v

libs/clk/rtl/clkgen_tds_io.v  \
libs/clk/rtl/clkgen_tds_io2x.v \

libs/clk/n2_clk_clstr_hdr_cust_l/n2_clk_clstr_hdr_cust/rtl/n2_clk_clstr_hdr_cust.v
libs/clk/n2_clk_pgrid_cust_l/n2_clk_tds_io_cust/rtl/n2_clk_tds_io_cust.v
libs/clk/n2_clk_pgrid_cust_l/n2_clk_tds_io2x_cust/rtl/n2_clk_tds_io2x_cust.v

libs/n2sram/compiler/physical/n2_com_dp_32x148s_cust_l/n2_com_dp_32x148s_cust/rtl/n2_com_dp_32x148s_cust.v
libs/n2sram/compiler/physical/n2_com_dp_64x148s_cust_l/n2_com_dp_64x148s_cust/rtl/n2_com_dp_64x148s_cust.v
libs/n2sram/dp/n2_niu_dp_256x152s_cust_l/n2_niu_dp_256x152s_cust/rtl/n2_niu_dp_256x152s_cust.v

design/sys/iop/niu/rtl/df1.v \
design/sys/iop/niu/rtl/dffe.v \
design/sys/iop/niu/rtl/dffr.v \
design/sys/iop/niu/rtl/dffre.v \

design/sys/iop/niu/rtl/niu_ram_256x148.v \
design/sys/iop/niu/rtl/niu_ram_256_148.v \
design/sys/iop/niu/rtl/txc_defines.h \
design/sys/iop/niu/rtl/niu_dmc_reg_defines.h \
design/sys/iop/niu/rtl/niu_tdmc.v \
design/sys/iop/niu/rtl/niu_dmc_txcif.v \
design/sys/iop/niu/rtl/niu_dmc_dmaarb.v \
design/sys/iop/niu/rtl/niu_dmc_txpios.v \
design/sys/iop/niu/rtl/niu_dmc_cache_dataFetch.v \
design/sys/iop/niu/rtl/niu_dmc_txcache.v \
design/sys/iop/niu/rtl/niu_tdmc_cachewrite.v \
design/sys/iop/niu/rtl/niu_tdmc_cacheread.v \
design/sys/iop/niu/rtl/niu_tdmc_addrcalc.v \
design/sys/iop/niu/rtl/niu_tdmc_cachefetch.v \
design/sys/iop/niu/rtl/niu_tdmc_dmacontext.v \
design/sys/iop/niu/rtl/niu_tdmc_cacheparity.v \
design/sys/iop/niu/rtl/niu_tdmc_debug.v \
design/sys/iop/niu/rtl/niu_tdmc_dmaregs.v \
design/sys/iop/niu/rtl/niu_tdmc_mbox.v \
design/sys/iop/niu/rtl/niu_tdmc_mbox_context.v \
design/sys/iop/niu/rtl/niu_tdmc_piodecodes.v \
design/sys/iop/niu/rtl/niu_tdmc_reset.v \
design/sys/iop/niu/rtl/niu_tdmc_sendmbox.v \
design/sys/iop/niu/rtl/niu_tdmc_clkbuf.v \
design/sys/iop/niu/rtl/niu_mb2.v \

design/sys/iop/niu/rtl/niu_ram_32_146.v \
design/sys/iop/niu/rtl/niu_ram_64x146.v \
design/sys/iop/niu/rtl/niu_ram_64_146.v \
design/sys/iop/niu/rtl/niu_smx.v \
design/sys/iop/niu/rtl/niu_smx_stall_hdlr.v \
design/sys/iop/niu/rtl/niu_smx_ff_ctrl.v \
design/sys/iop/niu/rtl/niu_smx_ff_regfl.v \
design/sys/iop/niu/rtl/niu_smx_rdreq_dmc.v \
design/sys/iop/niu/rtl/niu_smx_regfl.v \
design/sys/iop/niu/rtl/niu_smx_req_ff.v \
design/sys/iop/niu/rtl/niu_smx_req_sii.v \
design/sys/iop/niu/rtl/niu_smx_req_sii_cr.v \
design/sys/iop/niu/rtl/niu_smx_resp_dmc.v \
design/sys/iop/niu/rtl/niu_smx_resp_ff.v \
design/sys/iop/niu/rtl/niu_smx_resp_rcvfile.v \
design/sys/iop/niu/rtl/niu_smx_resp_sio.v \
design/sys/iop/niu/rtl/niu_smx_sm_req_cmdreq.v \
design/sys/iop/niu/rtl/niu_smx_sm_req_datareq.v \
design/sys/iop/niu/rtl/niu_smx_sm_req_dv.v \
design/sys/iop/niu/rtl/niu_smx_sm_req_siiarb.v \
design/sys/iop/niu/rtl/niu_smx_sm_req_siireq.v \
design/sys/iop/niu/rtl/niu_smx_sm_resp_cmdlaunch.v \
design/sys/iop/niu/rtl/niu_smx_sm_resp_cmdproc.v \
design/sys/iop/niu/rtl/niu_smx_sm_resp_dv.v \
design/sys/iop/niu/rtl/niu_smx_wreq_dmc.v \
design/sys/iop/niu/rtl/niu_smx_xtb.v \
design/sys/iop/niu/rtl/niu_smx_ecc16_genpar.v \
design/sys/iop/niu/rtl/niu_smx_ecc16_corr.v \
design/sys/iop/niu/rtl/niu_smx_gen_siudp.v \
design/sys/iop/niu/rtl/niu_smx_regflag.v \
design/sys/iop/niu/rtl/niu_smx_status.v \
design/sys/iop/niu/rtl/niu_smx_timer.v \
design/sys/iop/niu/rtl/niu_smx_timeout_hdlr.v \
design/sys/iop/niu/rtl/niu_smx_arb_2c.v \
design/sys/iop/niu/rtl/niu_smx_decode.v \
design/sys/iop/niu/rtl/niu_smx_ff_ram32x144.v \
design/sys/iop/niu/rtl/niu_smx_pio.v \
design/sys/iop/niu/rtl/niu_mb0.v \

design/sys/iop/niu/rtl/niu_meta_arb_define.h \
design/sys/iop/niu/rtl/niu_meta_arb_dbg.v \
design/sys/iop/niu/rtl/niu_meta_rd_tagfifo.v \
design/sys/iop/niu/rtl/niu_meta_wr_tagfifo.v \
design/sys/iop/niu/rtl/niu_rd_meta_arb.v \
design/sys/iop/niu/rtl/niu_wr_meta_arb.v \
design/sys/iop/niu/rtl/niu_meta_arb_reset.v \
design/sys/iop/niu/rtl/niu_meta_arb_syncfifo.v \
design/sys/iop/niu/rtl/niu_meta_arb.v \

design/sys/iop/tds/rtl/tds_l2l1clk_io.v \
design/sys/iop/tds/rtl/dmo_regs.v \
design/sys/iop/tds/rtl/tds_n2_efuhdr2_msff_ctl_macro__width_4.v \
design/sys/iop/tds/rtl/tds_n2_efuhdr2_spare_ctl_macro__num_4.v \
design/sys/iop/tds/rtl/tds_n2_efuhdr2_msff_ctl_macro__en_1__width_5.v \
design/sys/iop/tds/rtl/tds_n2_efuhdr2_msff_ctl_macro__en_1__width_22.v \
design/sys/iop/tds/rtl/tds_n2_efuhdr2_ctl.v \
design/sys/iop/tds/rtl/tds.v \
}

set link_library [concat $link_library \
   dw_foundation.sldb \
]


set mix_files {}
set top_module tds

set include_paths {\
}

set black_box_libs {}
set black_box_designs {}
set mem_libs {}

set dont_touch_modules {\
n2_com_dp_32x148s_cust \
n2_com_dp_64x148s_cust \
n2_niu_dp_256x152s_cust \
}

set compile_effort   "medium"

set compile_flatten_all 1

set compile_no_new_cells_at_top_level false

set default_clk cmp_gclk_c0_tds
set default_clk_freq  1500
set default_setup_skew  0.0
set default_hold_skew  0.0
set default_clk_transition  0.05
set clk_list {                        \
                { cmp_gclk_c0_tds   1500.0   0.000   0.000   0.05}        \
}

set ideal_net_list {}
set false_path_list {}
set enforce_input_fanout_one     0
set allow_outport_drive_innodes  1
set skip_scan            0
set add_lockup_latch     false
set chain_count          1
set scanin_port_list     {}
set scanout_port_list    {}
set scanenable_port      global_shift_enable
set has_test_stub        1
set scanenable_pin       test_stub_no_bist/se
set long_chain_so_0_net  long_chain_so_0
set short_chain_so_0_net short_chain_so_0
set so_0_net             so_0
set insert_extra_lockup_latch 0
set extra_lockup_latch_clk_list {}