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.TH SCANTEST 1 "2003-07-24" "perl v5.8.0" "User Contributed Perl Documentation"
scantest \- Perl script for scan pattern generation.
scantest [options] gate_level_netlist
\&\*(L"scantest\*(R" is a front-end interface for use of the ScanTest
package for automatic test pattern generation using FastScan.
\&\*(L"scantest\*(R" controls the creation of the test procedure file,
FastScan command file and execution script, as well as the
generation and simulation of test patterns.
The intention behind \*(L"scantest\*(R" is to simplify the \s-1ATPG\s0 flow.
If a design file conforms to the built-in defaults the entire
flow can be run by specifying only the design file:
The default design settings are as follows:
.IP "\(bu one scan chain" 4
.IX Item "one scan chain"
.ie n .IP "\(bu clock port is named ""clk""" 4
.el .IP "\(bu clock port is named ``clk''" 4
.IX Item "clock port is named clk"
.ie n .IP "\(bu scanin port is named ""si""" 4
.el .IP "\(bu scanin port is named ``si''" 4
.IX Item "scanin port is named si"
.ie n .IP "\(bu scanout port is named ""so""" 4
.el .IP "\(bu scanout port is named ``so''" 4
.IX Item "scanout port is named so"
.ie n .IP "\(bu scanenable port is named ""se""" 4
.el .IP "\(bu scanenable port is named ``se''" 4
.IX Item "scanenable port is named se"
If the design does not conform to these defaults, switches
are available to modify the operation of \*(L"scantest\*(R".
Run atpg only. If the option is negated, only simulation
is performed. This is the same as specifying \*(L"\-sim\*(R"
.IP "\-bb or \-blackbox" 4
.IX Item "-bb or -blackbox"
Enable automatic black box recognition. Typically this option
should not be required. The switch can be used to force
continuation of the flow in the presence of missing cells.
Coverage is likely to be poor.
Before setting this switch the user is advised to check that
correct version of the library is being referenced and that
all verilog files have been specified.
In the event that a view is known to be missing (such as a
memory block) this switch will need to be specified.
Introduces a comma separated list of rising edge active clocks.
Default settings are overridden. Default names must be given
Specifies that the block has no sequential cells. Normally
\&\*(L"scantest\*(R" searches for the presence of default or user
specified clock ports. Specifying \*(L"\-comb\*(R" suppresses this
Optional switch that introduces a single design file.
Allows a non-default FastScan library to be specified.
The \s-1DFT\s0 library is normally \*(L"$LIBDIR/u1/atpg/u1.mdl\*(R".
This switch is provided for library debug purposes. Do not
use it in the normal flow!
If set, this switch causes only the FastScan command file
(dofile) to be generated.
If negated, the switch allows the flow to proceed without
generating a new default command file. The command file
should be already present. This switch allows the user
to develop a custom command file.
Allows a non-default dump directory to be specified.
By default, \*(L"scantest\*(R" creates a dump area for simulation
files in either \*(L"/export/home/bw\*(R" (scratch area available
when running under dream) or \*(L"/tmp\*(R". The user is free to
A subdirectory composed of the user's name and process
id is created into which the simulation files are dumped.
\&\s-1NOTE:\s0 The dump directory is never cleaned out. The user
is responsible for ensuring that unnecessary files are
Specifies verilog include files. This switch is necessary
if the design is spread over multiple files.
By default no include files are assumed.
Specifies an alternate name for the fastscan log file.
Prints the list of switches with brief descriptions and
Introduces a comma separated list of input ports which
need to be contrained high.
By default none are assumed.
Introduces a comma separated list of input ports which
need to be contrained low.
By default none are assumed.
Introduces a comma separated list of rising edge active clocks.
This switch is an alias for \*(L"clk\*(R".
Introduces a comma separated list of falling edge active clocks.
By default none are assumed.
If set, this switch causes only the FastScan run file to be
If negated, the switch allows the flow to proceed without
generating a new default run file. The run file needs to
be already present. This switch allows the user to invoke
FastScan with customized settings.
Introduces a comma separated list of scanenable ports.
Typically, only one scan enable port is expected. This
switch is provided to specify a non-default port name.
In the event that the default name, \*(L"se\*(R", is also required
it needs to be explicitly specified.
Introduces a comma separated list of scanin ports. The
default setting is overwritten. If the default name, \*(L"si\*(R",
is also required it needs to be explicitly specified.
The order of the scanin ports must match that of the
corresponding scanout ports.
.IX Item "-[no]simulation"
If set, this switch causes only simulation to be performed.
If negated, the switch halts the flow after pattern
Selects a 20 minute FastScan license. This works for small
jobs when no licence is available on the default large queue.
Introduces a comma separated list of scanout ports. The
default setting is overwritten. If the default name, \*(L"so\*(R",
is also required it needs to be explicitly specified.
The order of the scanout ports must match that of the
corresponding scanin ports.
If set, this switch causes only the FastScan test procedure
If negated, the switch allows the flow to proceed without
generating a new default test procedure file. The test
procedure file should be already present. This switch allows
the user to develop a custom protocol.
This switch specifies the name of the top module. By default
the top module name is taken from the root of the design
file. The switch is necessary if the top module name does
not match the design file name or if there are multiple top
If set, this switch will cause untestable fault information
to be added to the \s-1ATPG\s0 log file. If coverage is low, this
additional information could be large.
The \*(L"vverbose\*(R" flag adds instance coverage information to
the \s-1ATPG\s0 log file. If the design file contains a large number
of instances, printing the additional statistics slows down
the flow and increases the size of the log file.
Allows multiple design files and/or libraries to be listed
in a separate file. Internally this switch is used to reference
the m1 library (\*(L"$LIBDIR/m1/compiled/m1.vL\*(R"). If this switch
is used and the m1 library also needs to be referenced the
library must be explicitly specified.
\&\*(L"scantest\*(R" uses two environment variables:
Specifies the location of the design libraries.
Identifies where the default dump directory will be created.
\&\fIScanTest\fR\|(3), http://www.mentor.com/dft
Roger Mistely, <roger.mistely@sun.com>
projects / OpenSPARC-T2-DV / blob